公开(公告)号：US20220383931A1

公开(公告)日：2022-12-01

申请号：US17816138

申请日：2022-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G11C7/22 ,  G11C11/409 ,  G06F3/06

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20230274776A1

公开(公告)日：2023-08-31

申请号：US18314243

申请日：2023-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G11C11/409 ,  G06F3/0673 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0604 ,  G11C7/222

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20160164479A1

公开(公告)日：2016-06-09

申请号：US14959195

申请日：2015-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOON-JOO EOM ,  SEUNG-JUN BAE ,  DAE-SIK MOON ,  JOON-YOUNG PARK ,  MIN-SU AHN

IPC: H03F3/45 ,  H03D7/14

CPC classification number: H03D7/1441 ,  H03F3/45183 ,  H03F2203/45051 ,  H03F2203/45466 ,  H03F2203/45674 ,  H03F2203/45702 ,  H03K19/00361

Abstract: A buffer circuit includes a first differential amplifier, second differential amplifier, third differential amplifier, and mixer. The first differential amplifier generates a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal. The second differential amplifier generates a first signal based on the positive differential signal and the negative differential signal. The third differential amplifier generates a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal. The mixer outputs a signal, generated by mixing the first signal and the second signal, as an output signal.

Abstract translation: 缓冲电路包括第一差分放大器，第二差分放大器，第三差分放大器和混频器。 第一差分放大器基于输入信号和参考电压信号产生正差分信号和负差分信号。 第二差分放大器基于正差分信号和负差分信号产生第一信号。 第三差分放大器基于正差分信号和负差分信号产生具有与第一信号不同相位的第二信号。 混频器输出通过混合第一信号和第二信号而产生的信号作为输出信号。

公开(公告)号：US20240420754A1

公开(公告)日：2024-12-19

申请号：US18817678

申请日：2024-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G06F3/06 ,  G11C7/22 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20230317138A1

公开(公告)日：2023-10-05

申请号：US18330527

申请日：2023-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G11C7/22 ,  G06F3/06 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G11C7/222 ,  G06F3/0673 ,  G11C11/409 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0653

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20220093144A1

公开(公告)日：2022-03-24

申请号：US17539761

申请日：2021-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  KYUNG-SOO HA ,  YOUNG-SOO SOHN ,  KI-SEOK OH ,  CHANG-KYO LEE ,  JIN-HOON JANG ,  YEON-KYU CHOI ,  SEOK-HUN HYUN

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US20220122648A1

公开(公告)日：2022-04-21

申请号：US17564564

申请日：2021-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20210166749A1

公开(公告)日：2021-06-03

申请号：US17148915

申请日：2021-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20210082479A1

公开(公告)日：2021-03-18

申请号：US17104114

申请日：2020-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  KYUNG-SOO HA ,  YOUNG-SOO SOHN ,  KI-SEOK OH ,  CHANG-KYO LEE ,  JIN-HOON JANG ,  YEON-KYU CHOI ,  SEOK-HUN HYUN

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US20190237127A1

公开(公告)日：2019-08-01

申请号：US16230185

申请日：2018-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  Gil-Hoon Cha ,  Ki-Seok Oh ,  Chang-Kyo Lee ,  Yeon-Kyu Choi ,  Jung-Hwan Choi ,  Kyung-Soo Ha ,  Seok-Hun Hyun

IPC: G11C11/4076 ,  G11C11/409 ,  G06F3/06

CPC classification number: G11C11/4076 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/222 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.