公开(公告)号：US20130208546A1

公开(公告)日：2013-08-15

申请号：US13743412

申请日：2013-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SI-HONG KIM ,  SEUNG-JUN BAE ,  HYE-RAN KIM ,  HO-SEOK SEOL

IPC: G11C8/18 ,  G11C7/10

CPC classification number: G11C8/18 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/41 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2272

Abstract: A latency control circuit is configured to delay a read information signal in response to a CAS latency signal and an internal clock signal to generate a delayed read information signal, and is further configured to generate a latency control signal based on the delayed read information signal in response to a plurality of sampling control signals and a plurality of transfer control signals.

Abstract translation: 延迟控制电路被配置为响应于CAS等待时间信号和内部时钟信号而延迟读取信息信号，以产生延迟的读取信息信号，并且还被配置为基于延迟读取信息信号生成等待时间控制信号 响应于多个采样控制信号和多个传送控制信号。

公开(公告)号：US20180358060A1

公开(公告)日：2018-12-13

申请号：US15851197

申请日：2017-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANG-UHN CHA ,  YOUNG -HUN SEO ,  KWANG-IL PARK ,  SEUNG-JUN BAE

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  G06F11/10 ,  H03M13/00

CPC classification number: G11C7/1006 ,  G06F11/1044 ,  G06F11/1048 ,  G11C7/1018 ,  G11C7/106 ,  G11C7/1087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/05 ,  H03M13/611

Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.

公开(公告)号：US20160164479A1

公开(公告)日：2016-06-09

申请号：US14959195

申请日：2015-12-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOON-JOO EOM ,  SEUNG-JUN BAE ,  DAE-SIK MOON ,  JOON-YOUNG PARK ,  MIN-SU AHN

IPC: H03F3/45 ,  H03D7/14

CPC classification number: H03D7/1441 ,  H03F3/45183 ,  H03F2203/45051 ,  H03F2203/45466 ,  H03F2203/45674 ,  H03F2203/45702 ,  H03K19/00361

Abstract: A buffer circuit includes a first differential amplifier, second differential amplifier, third differential amplifier, and mixer. The first differential amplifier generates a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal. The second differential amplifier generates a first signal based on the positive differential signal and the negative differential signal. The third differential amplifier generates a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal. The mixer outputs a signal, generated by mixing the first signal and the second signal, as an output signal.

Abstract translation: 缓冲电路包括第一差分放大器，第二差分放大器，第三差分放大器和混频器。 第一差分放大器基于输入信号和参考电压信号产生正差分信号和负差分信号。 第二差分放大器基于正差分信号和负差分信号产生第一信号。 第三差分放大器基于正差分信号和负差分信号产生具有与第一信号不同相位的第二信号。 混频器输出通过混合第一信号和第二信号而产生的信号作为输出信号。