公开(公告)号：US20140313847A1

公开(公告)日：2014-10-23

申请号：US14250460

申请日：2014-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEONG-HWAN JEONG ,  YANG-KI KIM ,  SEOK-HUN HYUN ,  JUNG-HWAN CHOI

IPC: H03L7/08 ,  G11C8/18

CPC classification number: G11C8/18 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/095 ,  H03L7/10

Abstract: A clock synchronization circuit includes a delay-locked loop (DLL) and a delay-locked control unit. The DLL is configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal. The delay-locked control unit configured to detect the locked state of the DLL, and to control the DLL based on the determined locked state

Abstract translation: 时钟同步电路包括延迟锁定环（DLL）和延迟锁定控制单元。 DLL被配置为通过将输入时钟信号延迟延迟时间来产生输出时钟信号，并且执行延迟锁定操作，其中延迟时间根据输出时钟信号和 输入时钟信号。 所述延迟锁定控制单元被配置为检测所述DLL的锁定状态，并且基于所确定的锁定状态来控制所述DLL

公开(公告)号：US20230274776A1

公开(公告)日：2023-08-31

申请号：US18314243

申请日：2023-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G11C11/409 ,  G06F3/0673 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0604 ,  G11C7/222

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20220383931A1

公开(公告)日：2022-12-01

申请号：US17816138

申请日：2022-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G11C7/22 ,  G11C11/409 ,  G06F3/06

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20180374823A1

公开(公告)日：2018-12-27

申请号：US15995181

申请日：2018-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HOON SON ,  JUNG-HWAN CHOI ,  SEOK-HUN HYUN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/498

Abstract: A semiconductor package includes a first layer of one or more first semiconductor chips each having a first surface at which one or more first pads are exposed, a second layer of one or more second semiconductor chips disposed over the first layer and each having a second surface at which one or more second pads are exposed, and a first redistribution layer between the first layer and the second layer and electrically connected to the one or more first pads. The first layer may include one or more first TPVs extending through a substrate (panel) of the first layer and electrically connected to the first redistribution layer.

公开(公告)号：US20220122648A1

公开(公告)日：2022-04-21

申请号：US17564564

申请日：2021-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20210166749A1

公开(公告)日：2021-06-03

申请号：US17148915

申请日：2021-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G11C11/409 ,  G06F3/06 ,  G11C7/22

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20210082479A1

公开(公告)日：2021-03-18

申请号：US17104114

申请日：2020-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  KYUNG-SOO HA ,  YOUNG-SOO SOHN ,  KI-SEOK OH ,  CHANG-KYO LEE ,  JIN-HOON JANG ,  YEON-KYU CHOI ,  SEOK-HUN HYUN

IPC: G11C7/10 ,  G11C7/22

Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.

公开(公告)号：US20150147068A1

公开(公告)日：2015-05-28

申请号：US14552601

申请日：2014-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JEONG-KYOUM KIM ,  SEOK-HUN HYUN ,  IN-DAL SONG ,  SEONG-JIN JANG ,  JUNG-HWAN CHOI

IPC: H04B10/572

CPC classification number: H04B10/572 ,  H04B10/506 ,  H04B10/671 ,  H04B10/801 ,  H04J14/0278

Abstract: An optical transmission converter comprises a wavelength selector configured to output a reception wavelength selection signal and a transmission wavelength selection signal in response to a wavelength control signal, an opto-electrical converter configured to convert a selection optical signal into a reception electrical signal based on a reception optical signal from a host device and the reception wavelength selection signal, and an electro-optical converter configured to convert a transmission electrical signal into a transmission optical signal based on the transmission wavelength selection signal and the transmission electrical signal.

Abstract translation: 一种光传输转换器，包括：波长选择器，被配置为响应于波长控制信号输出接收波长选择信号和传输波长选择信号;光电转换器，被配置为基于选择光信号将选择光信号转换为接收电信号 接收光信号和接收波长选择信号，以及电光转换器，被配置为基于传输波长选择信号和传输电信号将传输电信号转换为传输光信号。

公开(公告)号：US20240420754A1

公开(公告)日：2024-12-19

申请号：US18817678

申请日：2024-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G06F3/06 ,  G11C7/22 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20230317138A1

公开(公告)日：2023-10-05

申请号：US18330527

申请日：2023-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G11C7/22 ,  G06F3/06 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G11C7/222 ,  G06F3/0673 ,  G11C11/409 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0653

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.