公开(公告)号：US20140313847A1

公开(公告)日：2014-10-23

申请号：US14250460

申请日：2014-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEONG-HWAN JEONG ,  YANG-KI KIM ,  SEOK-HUN HYUN ,  JUNG-HWAN CHOI

IPC: H03L7/08 ,  G11C8/18

CPC classification number: G11C8/18 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/095 ,  H03L7/10

Abstract: A clock synchronization circuit includes a delay-locked loop (DLL) and a delay-locked control unit. The DLL is configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal. The delay-locked control unit configured to detect the locked state of the DLL, and to control the DLL based on the determined locked state

Abstract translation: 时钟同步电路包括延迟锁定环（DLL）和延迟锁定控制单元。 DLL被配置为通过将输入时钟信号延迟延迟时间来产生输出时钟信号，并且执行延迟锁定操作，其中延迟时间根据输出时钟信号和 输入时钟信号。 所述延迟锁定控制单元被配置为检测所述DLL的锁定状态，并且基于所确定的锁定状态来控制所述DLL