公开(公告)号：US20170331476A1

公开(公告)日：2017-11-16

申请号：US15390851

申请日：2016-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEOK-JIN CHO ,  TAE-YOUNG OH

IPC: H03K19/00 ,  G11C7/10 ,  G11C5/14

CPC classification number: H03K19/0005 ,  G11C5/147 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/227 ,  G11C11/4093 ,  G11C29/021 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C2207/2254

Abstract: An impedance calibration circuit includes a first code generator, a first code storing circuit, a second code generator and a second code storing circuit. The first code generator generates a pull-up control code obtained from a result of comparing a target output high level (VOH) voltage with a first voltage of a first node. The first code storing circuit stores the pull-up control code when the target VOH voltage becomes the same as the first voltage. The second code generator generates a pull-down control code obtained from a result of comparing the VOH voltage with a second voltage of a second node. The second storing circuit stores the pull-down control code when the target VOH voltage becomes the same as the second voltage. The first code storing circuit and the second code storing circuit store pull-up control code and pull-down control code pairs respectively.

公开(公告)号：US20190027206A1

公开(公告)日：2019-01-24

申请号：US16039400

申请日：2018-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HWA KIM ,  TAE-YOUNG OH ,  JIN-HUN JANG ,  SEOK-JIN CHO ,  KYUNG-SOO HA

IPC: G11C11/4074 ,  G11C5/14

CPC classification number: G11C11/4074 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G11C5/147

Abstract: A memory device has a plurality of power rails, including: a first power rail for transmitting a high power voltage, a second power rail for transmitting a low power voltage, a third power rail for selectively receiving the high power voltage from the first power rail through a first dynamic voltage and frequency scaling (DVFS) switch and for selectively receiving the low power voltage from the second power rail through a second DVFS switch, a fourth power rail connected to a first power gating (PG) switch to selectively receive the high power voltage or the low power voltage from the third power rail, and a first circuit block connected to the fourth power rail to receive a power voltage to which the DVFS and PG are applied. When power gating is applied, supply of the power voltage to the fourth power rail is blocked.

公开(公告)号：US20190027195A1

公开(公告)日：2019-01-24

申请号：US15959344

申请日：2018-04-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HWA KIM ,  TAE-YOUNG OH ,  JIN-HOON JANG ,  SEOK-JIN CHO

IPC: G11C5/14

Abstract: A memory device having a plurality of voltage regions and a method of operating the same are provided. The memory device includes a memory cell array, a data path region including data processing blocks transmitting read/write data from/to the memory cell array during read/write operations, and a control signal path region including control blocks controlling the data processing blocks during the read/write operations. The data path region selectively receives a first high power voltage or a first low power voltage in accordance with an operating mode of the memory device. The control signal path region receives the first high power voltage regardless of the operating mode.