公开(公告)号：US10096453B2

公开(公告)日：2018-10-09

申请号：US15133989

申请日：2016-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijong Park ,  Jun-Youl Yang ,  Yongsun Ko ,  Kyunghyun Kim ,  Taeheon Kim ,  Jae Jin Shin

IPC: H01J37/32

Abstract: A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.

公开(公告)号：US09972638B2

公开(公告)日：2018-05-15

申请号：US14621568

申请日：2015-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghae Lee ,  Daehong Eom ,  JinGyun Kim ,  Daehyun Jang ,  Kihyun Hwang ,  Seongsoo Lee ,  Kyunghyun Kim ,  Chadong Yeo ,  Jun-Youl Yang ,  Se-Ho Cha

IPC: H01L21/8238 ,  H01L27/11582 ,  H01L29/78 ,  H01L21/283 ,  H01L21/311 ,  H01L27/11556 ,  H01L29/66

CPC classification number: H01L27/11582 ,  H01L21/283 ,  H01L21/311 ,  H01L27/11556 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/7827

Abstract: Three dimensional semiconductor memory devices and methods of fabricating the same are provided. According to the method, sacrificial layers and insulating layers are alternately and repeatedly stacked on a substrate, and a cutting region penetrating an uppermost sacrificial layer of the sacrificial layers is formed. The cutting region is filled with a non sacrificial layer. The insulating layers and the sacrificial layers are patterned to form a mold pattern. The mold pattern includes insulating patterns, sacrificial patterns, and the non sacrificial layer in the cutting region. The sacrificial patterns may be replaced with electrodes. The related semiconductor memory device is also provided.

公开(公告)号：US20180102235A1

公开(公告)日：2018-04-12

申请号：US15841230

申请日：2017-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijong Park ,  Jun-Youl Yang ,  Yongsun Ko ,  Kyunghyun Kim ,  Taeheon Kim ,  Jae Jin Shin

IPC: H01J37/32

CPC classification number: H01J37/32009 ,  H01J37/32449 ,  H01J37/32899 ,  H01J37/32926 ,  H01J37/32935 ,  H01J37/3299 ,  H01J2237/334

Abstract: A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.

公开(公告)号：US20240064979A1

公开(公告)日：2024-02-22

申请号：US18142191

申请日：2023-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woo Jun Park ,  Kyung Hyun Kim ,  Kun-Woo Park ,  Jun-Youl Yang ,  Dong Woo Lee ,  Sang Hyuk Hong

IPC: H10B43/27 ,  H10B80/00 ,  H10B43/10 ,  H10B43/40 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H01L25/065

CPC classification number: H10B43/27 ,  H10B80/00 ,  H10B43/10 ,  H10B43/40 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H01L25/0652

Abstract: A non-volatile memory device comprises a substrate, a mold structure that includes gate electrodes stacked on the substrate and mold insulating layers alternately stacked with the gate electrodes, a cell contact on the substrate, wherein the cell contact is electrically connected to a selection gate electrode of the gate electrodes and is not electrically connected to a non-selection gate electrode of the gate electrodes, an insulating ring on the substrate, wherein the insulating ring is between the non-selection gate electrode and a sidewall of the cell contact and is in contact with the non-selection gate electrode, and a high dielectric constant layer between respective ones of the gate electrodes and the mold insulating layers, wherein the insulating ring includes a first portion that overlaps the high dielectric constant layer in a vertical direction, and a second portion that does not overlap the high dielectric constant layer in the vertical direction.

公开(公告)号：US20150200112A1

公开(公告)日：2015-07-16

申请号：US14492122

申请日：2014-09-22

Applicant: Samsung Electronics Co., Ltd. ,  Soulbrain Co., Ltd.

Inventor： Hoon Han ,  Byoung-Moon Yoon ,  Young-Taek Hong ,  Keon-Young Kim ,  Jun-Youl Yang ,  Young-Ok Kim ,  Tae-Heon Kim ,  Sun-Joong Song ,  Jung-Hun Lim ,  Jae-Wan Park ,  Jin-Uk Lee

IPC: H01L21/3213 ,  H01L29/423 ,  C23F1/16 ,  H01L21/02

CPC classification number: H01L21/32133 ,  C09K13/04 ,  C23F1/26 ,  H01L21/32115 ,  H01L21/32134 ,  H01L27/11582 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/66666 ,  H01L29/7827

Abstract: The present disclosure herein relates to methods of forming conductive patterns and to methods of manufacturing semiconductor devices using the same. In some embodiments, a method of forming a conductive pattern includes forming a first conductive layer and a second conductive layer on a substrate. The first conductive layer and the second conductive layer may include a metal nitride and a metal, respectively. The first conductive layer and the second conductive layer may be etched using an etchant composition that includes phosphoric acid, nitric acid, an assistant oxidant and a remainder of water. The etchant composition may have substantially the same etching rate for the metal nitride and the metal.

Abstract translation: 本公开内容涉及形成导电图案的方法以及使用其形成半导体器件的方法。 在一些实施例中，形成导电图案的方法包括在衬底上形成第一导电层和第二导电层。 第一导电层和第二导电层可以分别包括金属氮化物和金属。 可以使用包括磷酸，硝酸，辅助氧化剂和剩余的水的蚀刻剂组合物来蚀刻第一导电层和第二导电层。 蚀刻剂组合物可以具有与金属氮化物和金属基本相同的蚀刻速率。

公开(公告)号：US20170207066A1

公开(公告)日：2017-07-20

申请号：US15133989

申请日：2016-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijong PARK ,  Jun-Youl Yang ,  Yongsun Ko ,  Kyunghyun Kim ,  Taeheon Kim ,  Jae Jin Shin

IPC: H01J37/32

CPC classification number: H01J37/32009 ,  H01J37/32449 ,  H01J37/32899 ,  H01J37/32926 ,  H01J37/32935 ,  H01J37/3299 ,  H01J2237/334

Abstract: A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.

公开(公告)号：US09530670B2

公开(公告)日：2016-12-27

申请号：US14492122

申请日：2014-09-22

Applicant: Samsung Electronics Co., Ltd. ,  Soulbrain Co., Ltd.

Inventor： Hoon Han ,  Byoung-Moon Yoon ,  Young-Taek Hong ,  Keon-Young Kim ,  Jun-Youl Yang ,  Young-Ok Kim ,  Tae-Heon Kim ,  Sun-Joong Song ,  Jung-Hun Lim ,  Jae-Wan Park ,  Jin-Uk Lee

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/3213 ,  H01L29/423 ,  C09K13/04 ,  C23F1/26 ,  H01L21/321 ,  H01L27/115 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/32133 ,  C09K13/04 ,  C23F1/26 ,  H01L21/32115 ,  H01L21/32134 ,  H01L27/11582 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/66666 ,  H01L29/7827

Abstract: The present disclosure herein relates to methods of forming conductive patterns and to methods of manufacturing semiconductor devices using the same. In some embodiments, a method of forming a conductive pattern includes forming a first conductive layer and a second conductive layer on a substrate. The first conductive layer and the second conductive layer may include a metal nitride and a metal, respectively. The first conductive layer and the second conductive layer may be etched using an etchant composition that includes phosphoric acid, nitric acid, an assistant oxidant and a remainder of water. The etchant composition may have substantially the same etching rate for the metal nitride and the metal.

Abstract translation: 本公开内容涉及形成导电图案的方法以及使用其形成半导体器件的方法。 在一些实施例中，形成导电图案的方法包括在衬底上形成第一导电层和第二导电层。 第一导电层和第二导电层可以分别包括金属氮化物和金属。 可以使用包括磷酸，硝酸，辅助氧化剂和剩余的水的蚀刻剂组合物来蚀刻第一导电层和第二导电层。 蚀刻剂组合物可以具有与金属氮化物和金属基本相同的蚀刻速率。

公开(公告)号：US10580617B2

公开(公告)日：2020-03-03

申请号：US15841230

申请日：2017-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kijong Park ,  Jun-Youl Yang ,  Yongsun Ko ,  Kyunghyun Kim ,  Taeheon Kim ,  Jae Jin Shin

IPC: H01J37/32

Abstract: A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.