MEMORY DEVICE INCLUDING BIT LINE SENSE AMPLIFIER FOR CONSTANTLY CONTROLLING SENSING OPERATION

    公开(公告)号:US20190096446A1

    公开(公告)日:2019-03-28

    申请号:US15941877

    申请日:2018-03-30

    Abstract: A memory device includes memory cell blocks, bit line sense amplifier blocks, and a control circuit connected to one or more of the bit line sense amplifier blocks arranged between the memory cell blocks. The control circuit controls levels of currents respectively supplied to a first sensing driving voltage line and a second sensing driving voltage line driving bit line sense-amplifiers, to be constant. A first sensing driving control signal and/or a second sensing driving control signal, output from the sensing-matching control circuit is provided to the bit line sense amplifiers in all of the bit line sense amplifier blocks, so that the bit line sense amplifiers are constantly driven based on the constant levels of currents supplied to the first sensing driving voltage line and the second sensing driving voltage line.

    Semiconductor device for controlling power-up sequences

    公开(公告)号:US09755503B2

    公开(公告)日:2017-09-05

    申请号:US15212614

    申请日:2016-07-18

    CPC classification number: H02M1/36 G11C5/025 G11C5/148 H01L25/0657

    Abstract: A semiconductor device for controlling a power-up sequence is provided. The semiconductor device includes a plurality of chips. Each of the chips includes a power-up sequence controller configured to differently control generation sequences of internal source voltages. The power-up sequence controller changes the generation sequences of the internal source voltages in response to a power stabilization signal which is generated according to an external source voltage applied thereto in powering up the semiconductor device. Accordingly, a power-up current which is generated according to the internal source voltages being generated has a peak current distribution where a peak current may be equally distributed.

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