公开(公告)号：US10056479B2

公开(公告)日：2018-08-21

申请号：US14993108

申请日：2016-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun Yoo ,  Jin-Hyun Noh ,  Kee-Moon Chun ,  Jong-Sung Jeon

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7816 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/165 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device has reduced ON resistance (Ron) as well as a reduced electric field emanating from a current path. The semiconductor device includes a fin pattern, a gate electrode intersecting the fin pattern, a source region which has a first conductivity type and is disposed on one side of the gate electrode, a body region which has a second conductivity type, is situated within the fin pattern under the source region, and extends in a loop around the source region, a drain region which has the first conductivity type and is disposed on the other side of the gate electrode, a field dispersion region which has the second conductivity type and is situated within the fin pattern between the gate electrode and the drain region, and a drift region which has the first conductivity type, is situated within the fin pattern under the drain region and the field dispersion region, and extends in a loop around the drain region and the field dispersion region.

公开(公告)号：US10318678B2

公开(公告)日：2019-06-11

申请号：US14254337

申请日：2014-04-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wook Lee ,  Han-Gu Kim ,  Young-Keun Lee ,  Jong-Sung Jeon

IPC: G06F17/50

Abstract: A three-dimensional optoelectrical simulation includes generating a process simulation result including a doping profile of a silicon substrate of image sensor, a structure simulation result with respect to a back end of line structure, and a merged result generated by merging a process simulation result and a structure simulation result, selectively extending the merged result to an extended result by using a process simulation result or a structure simulation result, generating a segmented result for each pixel based on a merged result or an extended result, an optical crosstalk simulation result of image sensor based on a structure simulation result and an optical mesh, and a final simulation result including an electrical crosstalk simulation result of the image sensor based on a segmented result for each pixel and an optical crosstalk simulation result.

公开(公告)号：US09548401B2

公开(公告)日：2017-01-17

申请号：US14698909

申请日：2015-04-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun Yoo ,  Jin-Hyun Noh ,  Su-Tae Kim ,  Byeong-Ryeol Lee ,  Seong-Hun Jang ,  Jong-Sung Jeon

IPC: H01L29/02 ,  H01L29/94 ,  H01L29/78 ,  H01L27/06 ,  H01L29/10

CPC classification number: H01L29/94 ,  H01L27/0629 ,  H01L29/1041 ,  H01L29/7833 ,  H01L29/7838 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate including a first impurity diffusion region having a first doping concentration and at least one second impurity diffusion region having a second doping concentration different from the first doping concentration, the at least one second impurity region being surrounded by the first impurity diffusion region; at least one electrode facing the first impurity diffusion region and the at least one second impurity diffusion region; and at least one insulating layer between the first impurity diffusion region and the at least one electrode, and between the at least one second impurity diffusion region and the at least one electrode.

Abstract translation: 一种半导体器件包括：衬底，其包括具有第一掺杂浓度的第一杂质扩散区域和具有不同于第一掺杂浓度的第二掺杂浓度的至少一个第二杂质扩散区域，所述至少一个第二杂质区域被第一杂质包围 扩散区; 面向所述第一杂质扩散区域和所述至少一个第二杂质扩散区域的至少一个电极; 以及在所述第一杂质扩散区域和所述至少一个电极之间以及所述至少一个第二杂质扩散区域和所述至少一个电极之间的至少一个绝缘层。

公开(公告)号：US09324832B1

公开(公告)日：2016-04-26

申请号：US14856666

申请日：2015-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang-Hyun Baek ,  Kwan-Jae Song ,  Jong-Sung Jeon

IPC: H01L21/3205 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/66818

Abstract: In a method, a dummy gate layer structure and a mask layer are formed on a substrate. The mask layer is patterned to form masks. Spacers are formed on sidewalls of the mask. A dummy gate mask is formed between the spacers. The dummy gate layer structure is patterned using the dummy gate mask to form dummy gate structures. The dummy gate structure is replaced with a gate structure. When the mask is formed, an initial layout of masks extending in a first direction is designed. An offset bias in a second direction is provided for a specific region of the initial layout to design a final layout having a width in the second direction varying along the first direction. The mask layer is patterned according to the final layout to form the masks having a width varying along the first direction.

Abstract translation: 在一种方法中，在基板上形成伪栅极层结构和掩模层。 将掩模层图案化以形成掩模。 垫片形成在面罩的侧壁上。 在间隔件之间形成虚拟栅极掩模。 使用伪栅极掩模对虚拟栅极层结构进行图案化以形成伪栅极结构。 虚拟栅极结构被栅极结构代替。 当形成掩模时，设计沿第一方向延伸的掩模的初始布局。 针对初始布局的特定区域提供第二方向上的偏移偏移，以设计沿着第一方向具有沿第二方向的宽度变化的最终布局。 根据最终布局图案化掩模层以形成具有沿着第一方向变化的宽度的掩模。

公开(公告)号：US09935167B2

公开(公告)日：2018-04-03

申请号：US15268833

申请日：2016-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Hyun Noh ,  Su-Tae Kim ,  Jae-Hyun Yoo ,  Byeong-Ryeol Lee ,  Jong-Sung Jeon

IPC: H01L29/00 ,  H01L29/06 ,  H01L29/78 ,  H01L29/161 ,  H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L27/092 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/063 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/408 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7851

Abstract: Semiconductor devices include a channel layer on a substrate, the channel layer including a material having a lattice constant different from a lattice constant of the substrate, a first gate electrode on the channel layer, a first source region of a first conductivity type at a first side of the first gate electrode, a first body region of a second conductivity type under the first source region and contacting the first source region, a first drain region of the first conductivity type disposed at a second side of the first gate electrode, a first drift region of the first conductivity type under the first drain region and contacting the first drain region, and a first stud region in the channel layer and the first drift region. The first stud region has an impurity concentration higher than an impurity concentration of the first drift region.

公开(公告)号：US09679886B2

公开(公告)日：2017-06-13

申请号：US14509365

申请日：2014-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun Yoo ,  Jin-Tae Kim ,  Jong-Sung Jeon

IPC: H01L27/02 ,  H01L27/06

CPC classification number: H01L27/0266 ,  H01L27/0248 ,  H01L27/0285 ,  H01L27/0288 ,  H01L27/0629

Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a plurality of active fins and a plurality of grooves. The ESD protection device includes an insulation layer on the active fins and the grooves, and a gate electrode on the active fins. The ESD protection device includes a first impurity region adjacent to a first side of the gate electrode, and a second impurity region adjacent to a second side of the gate electrode. The second side of the gate electrode may be arranged opposite to the first side. The ESD protection device includes an electrode pattern of a capacitor overlapping the first impurity region, a resistor overlapping the second impurity region, and a connection structure electrically connecting the electrode pattern, the gate electrode, and the resistor to each other.

公开(公告)号：US10186505B2

公开(公告)日：2019-01-22

申请号：US15603969

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun Yoo ,  Jin-Tae Kim ,  Jong-Sung Jeon

IPC: H01L27/02 ,  H01L27/06

Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a plurality of fins extending in a first direction, with an insulation layer on the fins. A gate electrode extending in a second direction, an electrode pattern of a capacitor, and a resistor are on the insulation layer. A drain is on a first side of the gate electrode, and a source is on a second side of the gate electrode. A connection structure electrically connects the electrode pattern, the gate electrode and the resistor. The electrode pattern is on the first side or the second side of the gate electrode, and the resistor is on the other of the first side or the second side. At least a portion of the resistor extends in the second direction.