公开(公告)号：US20240079311A1

公开(公告)日：2024-03-07

申请号：US18229035

申请日：2023-08-01

Applicant: SAMSUNG ELECTRONICS CO.,LTD

Inventor： Seung Hyun CHO ,  Jeong-Kyu Ha ,  Jae-Min Jung

IPC: H01L23/498 ,  B32B7/12 ,  B32B27/06

CPC classification number: H01L23/4985 ,  B32B7/12 ,  B32B27/06 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16225

Abstract: A semiconductor package includes a film substrate; a wiring layer provided on the film substrate; and a semiconductor chip provided on the wiring layer and electrically connected to the wiring layer. The film substrate includes a first layer, wherein the first layer is an insulating layer having the wiring layer thereon. The film substrate further includes a second layer, wherein the second layer is attached to a bottom of the first layer and comprises a gas. The second layer is configured to be peeled off of the first layer.

公开(公告)号：US09280182B2

公开(公告)日：2016-03-08

申请号：US14195352

申请日：2014-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-Kyu Ha ,  Kwan-Jai Lee ,  Jae-Min Jung ,  Kyong-Soon Cho ,  Na-Rae Shin ,  Kyoung-Suk Yang ,  Pa-Lan Lee ,  So-Young Lim

IPC: H01L29/18 ,  G06F1/16 ,  G06F3/041 ,  H01L27/32

CPC classification number: G06F3/0412 ,  G06F1/1626 ,  G06F1/1637 ,  G06F1/1643 ,  G06F1/1652 ,  G06F3/0416 ,  G06F2203/04102 ,  H01L27/323 ,  H01L27/3276 ,  H01L2251/5338

Abstract: A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads.

Abstract translation: 薄膜封装上的芯片包括柔性基膜，其具有彼此相对的第一表面和第二表面，所述第一表面和第二表面在其中包括至少一个通孔，分别设置在基膜的第一表面和第二表面上的多个布线 ，其包括通过所述至少一个通孔彼此连接的第一引线和第二引线，以及显示面板驱动芯片和触摸面板传感器芯片，每个安装在所述第一引线和所述第二表面中的任何一个上 其中所述显示面板驱动面板和所述触摸面板传感器芯片中的至少一个电连接到所述第一和第二引线。

公开(公告)号：US09059162B2

公开(公告)日：2015-06-16

申请号：US13933185

申请日：2013-07-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Kyu Ha ,  Kwan-Jai Lee ,  Jae-Min Jung ,  Kyong-Soon Cho ,  Na-Rae Shin ,  Kyoung-Suk Yang ,  Pa-Lan Lee ,  So-Young Lim

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A COF substrate may include a base film, first upper conductive patterns, at least one second upper conductive pattern and lower conductive patterns. The first upper conductive patterns may be arranged on an upper surface of the base film. Each of the first upper conductive patterns may have an inner pattern and an outer pattern spaced apart from each other. The second upper conductive pattern may be arranged on the upper surface of the base film between the first upper conductive patterns. The lower conductive patterns may be arranged on a lower surface of the base film. The lower conductive patterns may be electrically connected between the inner pattern and the outer pattern. Thus, conductive materials causing a short between the panel patterns may not exist between the inner pattern and the outer pattern on the upper surface of the base film.

Abstract translation: COF基板可以包括基膜，第一上导电图案，至少一个第二上导电图案和下导电图案。 第一上导电图案可以布置在基膜的上表面上。 每个第一上导电图案可以具有彼此间隔开的内图案和外图案。 第二上导电图案可以布置在第一上导电图案之间的基膜的上表面上。 下导电图案可以布置在基膜的下表面上。 下部导电图案可以电连接在内部图案和外部图案之间。 因此，在基片的上表面上的内图案和外图案之间可能不存在在面板图案之间引起短路的导电材料。

公开(公告)号：US20140246687A1

公开(公告)日：2014-09-04

申请号：US14195352

申请日：2014-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeong-Kyu Ha ,  Kwan-Jai Lee ,  Jae-Min Jung ,  Kyong-Soon Cho ,  Na-Rae Shin ,  Kyoung-Suk Yang ,  Pa-Lan Lee ,  So-Young Lim

IPC: H01L27/32

CPC classification number: G06F3/0412 ,  G06F1/1626 ,  G06F1/1637 ,  G06F1/1643 ,  G06F1/1652 ,  G06F3/0416 ,  G06F2203/04102 ,  H01L27/323 ,  H01L27/3276 ,  H01L2251/5338

Abstract: A chip on film package includes a flexible base film having a first surface and a second surface opposite to each other that includes at least one through hole therein, a plurality of wirings disposed on the first surface and the second surface of the base film, respectively, that include a first lead and a second lead connected to each other through the at least one through hole, and a display panel driving chip and a touch panel sensor chip, each mounted on any one of the first surface and the second surface of the base film, wherein at least one of the display panel driving panel and the touch panel sensor chip is electrically connected to the first and second leads.

Abstract translation: 薄膜封装上的芯片包括柔性基膜，其具有彼此相对的第一表面和第二表面，所述第一表面和第二表面在其中包括至少一个通孔，分别设置在基膜的第一表面和第二表面上的多个布线 ，其包括通过所述至少一个通孔彼此连接的第一引线和第二引线，以及显示面板驱动芯片和触摸面板传感器芯片，每个安装在所述第一引线和所述第二表面中的任何一个上 其中所述显示面板驱动面板和所述触摸面板传感器芯片中的至少一个电连接到所述第一和第二引线。

公开(公告)号：US10304764B2

公开(公告)日：2019-05-28

申请号：US15465146

申请日：2017-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yechung Chung ,  Woonbae Kim ,  Soyoung Lim ,  Jeong-Kyu Ha

IPC: H01L23/498 ,  H01L23/00

Abstract: In an embodiment, the film product includes a film substrate having a first surface and a second surface opposite the first surface. The film substrate has a length in a first direction and a width in a second direction perpendicular to the first direction. A first plurality of pads is on one of the first surface and the second surface, and the first plurality of pads is arranged in a third direction, the third direction being diagonal with respect to at least one of the first direction and the second direction. At least one merge line is electrically connecting at least two of the first plurality of pads.

公开(公告)号：US09620389B2

公开(公告)日：2017-04-11

申请号：US14967490

申请日：2015-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Kyu Ha ,  Youngshin Kwon ,  KwanJai Lee ,  Jae-Min Jung ,  KyongSoon Cho ,  Sang-Uk Han

IPC: H01L23/14 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/10 ,  H01L23/00 ,  H01L23/495 ,  H05K3/00 ,  H01L21/56 ,  H01L21/78 ,  H05K1/18 ,  H05K3/42

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/78 ,  H01L23/145 ,  H01L23/49524 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/50 ,  H01L2924/12042 ,  H05K1/114 ,  H05K1/115 ,  H05K1/189 ,  H05K3/0052 ,  H05K3/107 ,  H05K3/42 ,  H05K2203/1545 ,  Y10T156/1052 ,  H01L2924/00

Abstract: A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern.

公开(公告)号：US09349683B2

公开(公告)日：2016-05-24

申请号：US14714234

申请日：2015-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Min Jung ,  Jeong-Kyu Ha

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/4985 ,  G02F1/13452 ,  G02F1/13458 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/83 ,  H01L24/86 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81424 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/83104 ,  H01L2224/83862 ,  H01L2224/86203 ,  H01L2924/00014 ,  H05K1/028 ,  H05K1/112 ,  H05K1/118 ,  H05K1/189 ,  H05K2201/055 ,  H05K2201/09227 ,  H05K2201/10128 ,  H05K2201/10674 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A chip-on-film package comprises a film substrate comprising upper and lower surfaces, and a side having a bending part. A first output interconnection formed on the upper surface of the film substrate extends from a semiconductor chip disposed on the upper surface toward the bending part. A second output interconnection includes an upper output interconnection formed on the upper surface of the film substrate, and a lower output interconnection formed on the lower surface and extending onto the bending part. An input interconnection includes an upper input interconnection formed on the upper surface of the film substrate and a lower input interconnection formed on the lower surface and extending away from the bending part. Through-vias are formed to pass through the film substrate and electrically connect the upper output interconnection to the lower output interconnection, and the upper input interconnection to the lower input interconnection.

Abstract translation: 片上胶卷包装包括一个包括上表面和下表面的薄膜基材和一个具有弯曲部分的一面。 形成在薄膜基板的上表面上的第一输出互连件从设置在上表面上的半导体芯片朝向弯曲部分延伸。 第二输出互连包括形成在薄膜基板的上表面上的上输出互连和形成在下表面上并延伸到弯曲部上的下输出互连。 输入互连包括形成在薄膜基板的上表面上的上输入互连和形成在下表面上并且远离弯曲部延伸的下输入互连。 通孔形成为通过薄膜基板并将上部输出互连电连接到下部输出互连，并将上部输入互连电连接到下部输入互连。

公开(公告)号：US08853694B2

公开(公告)日：2014-10-07

申请号：US13669031

申请日：2012-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uk Han ,  Jeong-Kyu Ha ,  Young-Shin Kwon ,  Seung-Hwan Kim ,  Kwan-Jai Lee

IPC: H01L23/58 ,  H01L23/498 ,  H01L23/495 ,  H01L21/66 ,  H01L23/14

CPC classification number: H01L23/49524 ,  H01L22/32 ,  H01L23/145 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/29099 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern.

Abstract translation: 提供了一种薄膜（COF）封装和具有该芯片的半导体。 所述COF封装可以包括柔性膜，所述柔性膜具有与所述第一表面和所述第二表面相对并彼此相对并且包括从所述第一表面穿过所述第二表面的导电通孔，所述第一和第二导电图案分别位于所述第一表面和所述第二表面上， 集成电路（IC）芯片在第一表面上并与第一导电图案电连接，测试焊盘与导电通孔重叠并且电连接到第一导电 图案和第二导电图案，并且外部连接图案在与导电通孔间隔开的第二表面上并电连接到第二导电图案。

公开(公告)号：US20130175528A1

公开(公告)日：2013-07-11

申请号：US13669031

申请日：2012-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uk Han ,  Jeong-Kyu Ha ,  Young-Shin Kwon ,  Seung-Hwan Kim ,  Kwan-Jai Lee

IPC: H01L23/485

CPC classification number: H01L23/49524 ,  H01L22/32 ,  H01L23/145 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/29099 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Provided are a chip on film (COF) package and semiconductor having the same. The COF package can include a flexible film having first and second surfaces opposite to and facing each other and including a conductive via penetrating from the first surface to the second surface, first and second conductive patterns respectively is on the first surface and the second surface and electrically connected to each other through the conductive via, an integrated circuit (IC) chip is on the first surface and electrically connected to the first conductive pattern, a test pad overlaps the conductive via and is electrically connected to at least one of the first conductive pattern and the second conductive pattern, and an external connection pattern is on the second surface spaced apart from the conductive via and electrically connected to the second conductive pattern.

Abstract translation: 提供了一种薄膜（COF）封装和具有该芯片的半导体。 所述COF封装可以包括柔性膜，所述柔性膜具有与所述第一表面和所述第二表面相对并彼此相对并且包括从所述第一表面穿过所述第二表面的导电通孔，所述第一和第二导电图案分别位于所述第一表面和所述第二表面上， 集成电路（IC）芯片在第一表面上并与第一导电图案电连接，测试焊盘与导电通孔重叠并且电连接到第一导电 图案和第二导电图案，并且外部连接图案在与导电通孔间隔开的第二表面上并电连接到第二导电图案。

公开(公告)号：US11830803B2

公开(公告)日：2023-11-28

申请号：US17699525

申请日：2022-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanjai Lee ,  Jae-Min Jung ,  Jeong-Kyu Ha ,  Sang-Uk Han

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/4985 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/73 ,  H01L2224/73204

Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.