公开(公告)号：US10304764B2

公开(公告)日：2019-05-28

申请号：US15465146

申请日：2017-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yechung Chung ,  Woonbae Kim ,  Soyoung Lim ,  Jeong-Kyu Ha

IPC: H01L23/498 ,  H01L23/00

Abstract: In an embodiment, the film product includes a film substrate having a first surface and a second surface opposite the first surface. The film substrate has a length in a first direction and a width in a second direction perpendicular to the first direction. A first plurality of pads is on one of the first surface and the second surface, and the first plurality of pads is arranged in a third direction, the third direction being diagonal with respect to at least one of the first direction and the second direction. At least one merge line is electrically connecting at least two of the first plurality of pads.

公开(公告)号：US20250054825A1

公开(公告)日：2025-02-13

申请号：US18427051

申请日：2024-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyun LIM ,  Youngjun Yoon ,  Yechung Chung ,  Inho Choi

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L23/64 ,  H01L25/18

Abstract: An embodiment provides a semiconductor package including: a substrate having a first surface and a second surface disposed in an opposite direction to the first surface; a semiconductor chip disposed on at least one surface of the substrate; an electronic device disposed on the second surface of the substrate; a first molding layer disposed on the first surface of the substrate; and a second molding layer disposed on the second surface of the substrate, wherein the second molding layer has an open hole that exposes at least a portion of the electronic device to the outside, and a material of the second molding layer is located on an inner surface of the open hole.

公开(公告)号：US11862548B2

公开(公告)日：2024-01-02

申请号：US17340280

申请日：2021-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoungsuk Yang ,  Soyoung Lim ,  Yechung Chung

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/66 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L21/481 ,  H01L21/486 ,  H01L22/14 ,  H01L23/49827 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/4985 ,  H01L23/5387 ,  H01L25/18

Abstract: A package substrate film including a film substrate including upper and lower surfaces; a test pattern including an upper test line pattern extending on the upper surface of the film substrate; a lower test line pattern extending on the lower surface of the film substrate; a first test via pattern penetrating the film substrate and connecting the upper test line pattern to the lower test line pattern; a second test via pattern penetrating the film substrate outside the first test via pattern and connecting the upper test line pattern to the lower test line pattern; and a test pad between the first test via pattern and the second test via pattern, the test pad including first test pad at an outer side of the first test via pattern; and second test pad at an inner side of the second test via pattern and facing the first test pad.

公开(公告)号：US10741628B2

公开(公告)日：2020-08-11

申请号：US15653117

申请日：2017-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhwa Jang ,  Jungeun Koo ,  Yechung Chung

IPC: H01L27/32 ,  G09G3/20 ,  G09G3/3225 ,  H01L51/00

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate, a controller on the substrate, first and second drive circuits on the substrate, and a plurality of signal lines on the substrate that connect the controller to the first and second drive circuits. The plurality of signal lines are each at the same vertical level and are horizontally spaced apart from each other. Related printed circuit boards are also provided.

公开(公告)号：US20230077996A1

公开(公告)日：2023-03-16

申请号：US18051141

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungeun Koo ,  Yechung Chung

IPC: H01L23/498 ,  H01L21/66 ,  H01L23/00 ,  H01L23/49 ,  H01L25/07

Abstract: A chip-on-film package includes a base film having a top surface and a bottom surface, and a circuit region; a source driver chip and a gate driver chip mounted on the circuit region; a first conductive line on the top surface of the base film, a second conductive line on the bottom surface of the base film, and a conductive via that connects the first and second conductive lines to each other; a first row of bonding pads on the circuit region and connected to the source driver chip; a second row of bonding pads on the circuit region and connected to the source driver chip and the gate driver chip; and a test pad outside the circuit region and connected to the first and second conductive lines and the conductive via.

公开(公告)号：US20210074622A1

公开(公告)日：2021-03-11

申请号：US16874120

申请日：2020-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungeun Koo ,  Yechung Chung

IPC: H01L23/498 ,  H01L21/66 ,  H01L23/00

Abstract: A chip-on-film package includes a base film having a top surface and a bottom surface, and a circuit region; a source driver chip and a gate driver chip mounted on the circuit region; a first conductive line on the top surface of the base film, a second conductive line on the bottom surface of the base film, and a conductive via that connects the first and second conductive lines to each other; a first row of bonding pads on the circuit region and connected to the source driver chip; a second row of bonding pads on the circuit region and connected to the source driver chip and the gate driver chip; and a test pad outside the circuit region and connected to the first and second conductive lines and the conductive via.

公开(公告)号：US20240321902A1

公开(公告)日：2024-09-26

申请号：US18612828

申请日：2024-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Narae Shin ,  Jeongkyu Ha ,  Woonbae Kim ,  Yechung Chung ,  Jaemin Jung

IPC: H01L27/12

CPC classification number: H01L27/124

Abstract: A chip of film package comprises a film substrate having a chip mounting region, an inner lead bonding region arranged within the chip mounting region, and an outer lead bonding region spaced apart from the inner lead bonding region in a first direction, and providing upper and lower surfaces opposite to each other, a first upper wiring pattern arranged on the upper surface of the film substrate and extending in the first direction from the inner lead bonding region to the outer lead bonding region, a second upper wiring pattern spaced apart from the first upper wiring pattern in the first direction, an upper solder resist layer covering an upper surface of the first upper wiring pattern; and a lower solder resist layer covering an upper surface of the lower wiring pattern.

公开(公告)号：US11508651B2

公开(公告)日：2022-11-22

申请号：US16874120

申请日：2020-05-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungeun Koo ,  Yechung Chung

IPC: H01L23/498 ,  H01L21/66 ,  H01L23/00 ,  H01L23/49 ,  H01L25/07 ,  H01L23/538

Abstract: A chip-on-film package includes a base film having a top surface and a bottom surface, and a circuit region; a source driver chip and a gate driver chip mounted on the circuit region; a first conductive line on the top surface of the base film, a second conductive line on the bottom surface of the base film, and a conductive via that connects the first and second conductive lines to each other; a first row of bonding pads on the circuit region and connected to the source driver chip; a second row of bonding pads on the circuit region and connected to the source driver chip and the gate driver chip; and a test pad outside the circuit region and connected to the first and second conductive lines and the conductive via.