公开(公告)号：US09620389B2

公开(公告)日：2017-04-11

申请号：US14967490

申请日：2015-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Kyu Ha ,  Youngshin Kwon ,  KwanJai Lee ,  Jae-Min Jung ,  KyongSoon Cho ,  Sang-Uk Han

IPC: H01L23/14 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K3/10 ,  H01L23/00 ,  H01L23/495 ,  H05K3/00 ,  H01L21/56 ,  H01L21/78 ,  H05K1/18 ,  H05K3/42

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/78 ,  H01L23/145 ,  H01L23/49524 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/50 ,  H01L2924/12042 ,  H05K1/114 ,  H05K1/115 ,  H05K1/189 ,  H05K3/0052 ,  H05K3/107 ,  H05K3/42 ,  H05K2203/1545 ,  Y10T156/1052 ,  H01L2924/00

Abstract: A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern.

公开(公告)号：US09241407B2

公开(公告)日：2016-01-19

申请号：US13747832

申请日：2013-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Kyu Ha ,  Youngshin Kwon ,  KwanJai Lee ,  Jae-Min Jung ,  KyongSoon Cho ,  Sang-Uk Han

IPC: H01L23/14 ,  H05K1/11 ,  H05K3/10 ,  H01L23/00 ,  H05K3/00 ,  H05K1/18 ,  H05K3/42

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/78 ,  H01L23/145 ,  H01L23/49524 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/50 ,  H01L2924/12042 ,  H05K1/114 ,  H05K1/115 ,  H05K1/189 ,  H05K3/0052 ,  H05K3/107 ,  H05K3/42 ,  H05K2203/1545 ,  Y10T156/1052 ,  H01L2924/00

Abstract: A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern.

Abstract translation: 提供包括绝缘图案的胶带包装; 绝缘图案中的通孔中的通孔接触; 从所述通孔接触延伸到所述绝缘图案的切割表面的第一互连图案; 以及连接到绝缘图案下方的通孔接点的第二互连图案。 第二互连图案平行于第一互连图案并与绝缘图案的切割表面间隔开。

公开(公告)号：US20130240917A1

公开(公告)日：2013-09-19

申请号：US13780648

申请日：2013-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyong soon Cho ,  KwanJai Lee ,  Jae-Min Jung ,  Jeong-Kyu Ha ,  Sang-Uk Han

IPC: H01L23/525 ,  H02H9/04

CPC classification number: H01L23/5256 ,  H01L23/4985 ,  H01L23/60 ,  H01L2924/0002 ,  H02H9/041 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package may include a base film having a first surface and a second surface opposite the first surface, an interconnection pattern on the first surface of the base film, and a ground layer on the second surface of the base film. The semiconductor package may further include a semiconductor chip on the first surface of the base film within the first region and a via contact plug in the second region that penetrates the base film and is configured to electrically connect the interconnection pattern with the ground layer when electrostatic discharge occurs through the via contact plug.

Abstract translation: 提供半导体封装。 半导体封装可以包括具有第一表面和与第一表面相对的第二表面的基膜，在基膜的第一表面上的互连图案和基膜的第二表面上的接地层。 所述半导体封装还可以包括在所述第一区域内的所述基膜的第一表面上的半导体芯片和穿过所述基膜的所述第二区域中的通孔接触插塞，并且被配置为当静电时将所述互连图案与所述接地层电连接 通过通孔接触插头发生放电。

公开(公告)号：US12191246B2

公开(公告)日：2025-01-07

申请号：US18505613

申请日：2023-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： KwanJai Lee ,  Jae-Min Jung ,  Jeong-Kyu Ha ,  Sang-Uk Han

IPC: H01L23/498 ,  H01L23/00

Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.

公开(公告)号：US09177904B2

公开(公告)日：2015-11-03

申请号：US13769520

申请日：2013-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Min Jung ,  Sang-Uk Han ,  KwanJai Lee ,  KyongSoon Cho ,  Jeong-Kyu Ha

IPC: G02F1/1343 ,  H01L23/498 ,  H01L51/52

CPC classification number: H01L25/167 ,  H01L23/49827 ,  H01L23/4985 ,  H01L27/323 ,  H01L27/3276 ,  H01L27/3288 ,  H01L51/52 ,  H01L51/524 ,  H01L2251/5338 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Chip-on-film packages and device assemblies including the same may be provided. The device assembly includes a film package including a semiconductor chip, a panel substrate connected to one end of the film package, a display panel disposed on the panel substrate, and a controlling part connected to another end of the film package. The film package includes a film substrate, a first wire disposed on a top surface of the film substrate, and a second wire disposed on a bottom surface of the film substrate.

Abstract translation: 可以提供包括其的片上胶片包装和装置组件。 该装置组件包括：薄膜封装，其包括半导体芯片，连接到薄膜封装的一端的面板基板，设置在面板基板上的显示面板，以及连接到薄膜封装的另一端的控制部件。 薄膜封装包括薄膜基板，设置在薄膜基板的顶表面上的第一布线和设置在薄膜基板的底表面上的第二布线。

公开(公告)号：US20130186680A1

公开(公告)日：2013-07-25

申请号：US13747832

申请日：2013-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Kyu Ha ,  Youngshin Kwon ,  KwanJai Lee ,  Jae-Min Jung ,  KyongSoon Cho ,  Sang-UK Han

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/78 ,  H01L23/145 ,  H01L23/49524 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/50 ,  H01L2924/12042 ,  H05K1/114 ,  H05K1/115 ,  H05K1/189 ,  H05K3/0052 ,  H05K3/107 ,  H05K3/42 ,  H05K2203/1545 ,  Y10T156/1052 ,  H01L2924/00

Abstract: A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern.

Abstract translation: 提供包括绝缘图案的胶带包装; 绝缘图案中的通孔中的通孔接触; 从所述通孔接触延伸到所述绝缘图案的切割表面的第一互连图案; 以及连接到绝缘图案下方的通孔接点的第二互连图案。 第二互连图案平行于第一互连图案并与绝缘图案的切割表面间隔开。