公开(公告)号：US20240244843A1

公开(公告)日：2024-07-18

申请号：US18618451

申请日：2024-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hyun CHO ,  Kwang Ho LEE ,  Ji Hwan YU ,  Jong Soo KIM

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

公开(公告)号：US20240079311A1

公开(公告)日：2024-03-07

申请号：US18229035

申请日：2023-08-01

Applicant: SAMSUNG ELECTRONICS CO.,LTD

Inventor： Seung Hyun CHO ,  Jeong-Kyu Ha ,  Jae-Min Jung

IPC: H01L23/498 ,  B32B7/12 ,  B32B27/06

CPC classification number: H01L23/4985 ,  B32B7/12 ,  B32B27/06 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16225

Abstract: A semiconductor package includes a film substrate; a wiring layer provided on the film substrate; and a semiconductor chip provided on the wiring layer and electrically connected to the wiring layer. The film substrate includes a first layer, wherein the first layer is an insulating layer having the wiring layer thereon. The film substrate further includes a second layer, wherein the second layer is attached to a bottom of the first layer and comprises a gas. The second layer is configured to be peeled off of the first layer.

公开(公告)号：US20240096904A1

公开(公告)日：2024-03-21

申请号：US18459766

申请日：2023-09-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Min JUNG ,  Seung Hyun CHO

IPC: H01L27/12

CPC classification number: H01L27/124

Abstract: A chip-on-film package includes: a lower base film including a first surface and a second surface, which are opposite to each other; an upper base film including a third surface and a fourth surface, which are opposite to each other, and is disposed on the lower base film; a first semiconductor chip mounted on the second surface of the lower base film; a second semiconductor chip mounted on the third surface of the upper base film; and an interposer film interposed between the lower and upper base films, wherein the second and third surfaces face each other.

公开(公告)号：US20230081495A1

公开(公告)日：2023-03-16

申请号：US17983520

申请日：2022-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hyun CHO ,  Kwang Ho Lee ,  Ji Hwan Yu ,  Jong Soo Kim

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

公开(公告)号：US20210313352A1

公开(公告)日：2021-10-07

申请号：US17354516

申请日：2021-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hyun CHO ,  Kwang Ho LEE ,  Ji Hwan YU ,  Jong Soo KIM

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is firmed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

公开(公告)号：US20200303412A1

公开(公告)日：2020-09-24

申请号：US16890400

申请日：2020-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hyun CHO ,  Kwang Ho LEE ,  Ji Hwan YU ,  Jong Soo KIM

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.