公开(公告)号：US20160149003A1

公开(公告)日：2016-05-26

申请号：US14855533

申请日：2015-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-In Choi ,  Wook-Je Kim ,  Baek-Hap Choi ,  Jin-Hee Han ,  Hyun-Gi Hong

IPC: H01L29/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/66 ,  H01L21/324

CPC classification number: H01L29/1054 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28525 ,  H01L21/324 ,  H01L21/76879 ,  H01L21/76886 ,  H01L21/76897 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/8258 ,  H01L29/6659 ,  H01L29/7834

Abstract: In methods of manufacturing a semiconductor device, a stress channel layer is formed on a semiconductor substrate. A first ion-implantation process is performed on the semiconductor substrate or the stress channel layer at a temperature ranging from about 100° C. to about 600° C. A gate structure is formed on the stress channel layer. A first source/drain region is formed at an upper portion of the stress channel layer adjacent to the gate structure.

Abstract translation: 在制造半导体器件的方法中，在半导体衬底上形成应力沟道层。 在约100℃至约600℃的温度范围内，在半导体衬底或应力沟道层上进行第一离子注入工艺。在应力沟道层上形成栅极结构。 第一源极/漏极区域形成在与栅极结构相邻的应力沟道层的上部。

公开(公告)号：US09812559B2

公开(公告)日：2017-11-07

申请号：US15236726

申请日：2016-08-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-In Choi ,  Bong-Soo Kim ,  Hyun-Seung Kim ,  Hyun-Gi Hong

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/08 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/66803 ,  H01L21/02175 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/2255 ,  H01L21/2256 ,  H01L29/0847 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method comprises forming an active fin extending along a first direction; forming a field insulating layer exposing an upper part of the active fin, along long sides of the active fin; forming a dummy gate pattern extending along a second direction intersecting the first direction, on the active fin; forming a spacer on at least one side of the dummy gate pattern; forming a liner layer covering the active fin exposed by the spacer and the dummy gate pattern; forming a dopant supply layer containing a dopant element, on the liner layer; and forming a doped region in the active fin along an upper surface of the active fin by heat-treating the dopant supply layer.