公开(公告)号：US09905664B2

公开(公告)日：2018-02-27

申请号：US15604646

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Namkoong ,  Dong-Kyum Kim ,  Jung-Hwan Kim ,  Jung Geun Jee ,  Han-Vit Yang ,  Ji-Man Yoo

IPC: H01L29/792 ,  H01L21/336 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: H01L29/42328 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7926

Abstract: A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.

公开(公告)号：US09853044B2

公开(公告)日：2017-12-26

申请号：US14995586

申请日：2016-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

IPC: H01L27/11582 ,  H01L29/792 ,  H01L21/28 ,  H01L27/1157 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28008 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/7926

Abstract: A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.

公开(公告)号：US09536896B2

公开(公告)日：2017-01-03

申请号：US14674583

申请日：2015-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon Lee ,  Jin-Gyun Kim ,  Hyun Namkoong ,  Ki-Hyun Hwang ,  Hun-Hyeong Lim ,  Dong-Kyum Kim

IPC: H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L29/4234 ,  H01L29/7889 ,  H01L29/7926

Abstract: A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.

Abstract translation: 具有垂直结构的非易失性存储器件包括半导体层，在半导体层上沿垂直方向延伸的侧壁绝缘层，并且具有一个或多个突出区域，在半导体层上沿垂直方向布置的第一控制栅电极 并且分别接触在半导体层上形成有一个或多个突起区域的侧壁绝缘层的一部分和在垂直方向上排列的第二控制栅电极，并分别接触一个或多个突出区域中的一个。

公开(公告)号：US09613800B2

公开(公告)日：2017-04-04

申请号：US14625388

申请日：2015-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Yong Go ,  Jin-Gyun Kim ,  Dong-Kyum Kim ,  Jung-Ho Kim ,  Koong-Hyun Nam ,  Sung-Hae Lee ,  Eun-Young Lee ,  Jung-Geun Jee ,  Eun-Yeoung Choi ,  Ki-Hyun Hwang

IPC: H01L21/02 ,  H01L21/687 ,  C23C16/01 ,  C23C16/40 ,  C23C16/455 ,  H01L27/11582

CPC classification number: H01L21/0228 ,  C23C16/01 ,  C23C16/40 ,  C23C16/45525 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/68771 ,  H01L27/11582

Abstract: In a method of forming an oxide layer of a semiconductor process, a preliminary precursor flow is provided on a substrate in a deposition chamber to form a preliminary precursor layer, a precursor flow and a first oxidizing agent flow are provided on the preliminary precursor layer alternately and repeatedly to form precursor layers and first oxidizing agent layers alternately stacked on the preliminary precursor layer, and a second oxidizing agent flow is provided on the precursor layer or the first oxidizing agent layer alternately stacked to form a second oxidizing agent layer.

公开(公告)号：US09257573B2

公开(公告)日：2016-02-09

申请号：US13949447

申请日：2013-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

IPC: H01L29/792 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28008 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/7926

Abstract: A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.

Abstract translation: 提供半导体器件。 半导体包括在基板上沿第一方向交替堆叠的多个层间绝缘层和多个栅电极。 多个层间绝缘层和多个栅电极构成在第一方向上延伸的侧面。 栅电介质层设置在侧表面上。 沟道图案设置在栅介质层上。 栅介质层包括保护图案，电荷陷阱层和隧穿层。 保护图案包括设置在多个栅电极的对应的栅电极上的部分。 电荷陷阱层设置在保护图案上。 隧道层设置在电荷陷阱层和沟道图案之间。 保护图案比电荷陷阱层更致密。