公开(公告)号：US09252031B2

公开(公告)日：2016-02-02

申请号：US14493379

申请日：2014-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hohyeuk Im ,  Jongkook Kim ,  Gowoon Seong ,  SeokWon Lee ,  Byoungwook Jang ,  Eunseok Cho

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/367 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1438 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/05599

Abstract: Provided is a semiconductor package including a lower package, an interposer on the lower package, and an upper package on the interposer. The lower package may include a lower package substrate, a lower semiconductor chip on the lower package substrate, and a lower heat-transfer layer on the lower semiconductor chip. The interposer may include an interposer substrate, first and second heat-transfer openings defined by recessed bottom and top surfaces, respectively, of the interposer substrate, an upper interposer heat-transfer pad disposed in the second heat-transfer opening, and an upper heat-transfer layer disposed on the upper interposer heat-transfer pad. The upper package may include an upper package substrate, an upper package heat-transfer pad, which may be disposed in a third heat-transfer opening defined by a recessed bottom surface of the upper package substrate, and an upper semiconductor chip disposed on the upper package substrate.

Abstract translation: 提供了一种半导体封装，其包括下封装，下封装上的插入件和插入件上的上封装。 下封装可以包括下封装衬底，下封装衬底上的下半导体芯片和下半导体芯片上的下传热层。 插入器可以包括插入器基板，分别由插入器基板的凹入的底部和顶部表面限定的第一和第二传热开口，设置在第二传热开口中的上插入件传热垫，以及上部热 - 转移层，设置在上部插入件传热垫上。 上封装可以包括上封装衬底，上封装传热垫，其可以设置在由上封装衬底的凹陷底表面限定的第三传热开口中，以及设置在上封装衬底上的上半导体芯片 封装衬底。

公开(公告)号：US11710673B2

公开(公告)日：2023-07-25

申请号：US17376883

申请日：2021-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Dongwook Kim ,  Hyunki Kim ,  Jongbo Shim ,  Jihwang Kim ,  Sungkyu Park ,  Yongkwan Lee ,  Byoungwook Jang

IPC: H01L23/12 ,  H01L23/538

CPC classification number: H01L23/12 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386

Abstract: A semiconductor package including a first package substrate, a first semiconductor chip on the first package substrate, a first conductive connector on the first package substrate and laterally spaced apart from the first semiconductor chip, an interposer substrate on the first semiconductor chip and electrically connected to the first package substrate through the first conductive connector, the interposer substrate including a first portion overlapping the first semiconductor chip and a plurality of upper conductive pads in the first portion, a plurality of spacers on a lower surface of the first portion of the interposer substrate and positioned so as not to overlap the plurality of upper conductive pads in a plan view, and an insulating filler between the interposer substrate and the first package substrate may be provided.

公开(公告)号：US20240213174A1

公开(公告)日：2024-06-27

申请号：US18515797

申请日：2023-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junghoon Kang ,  Unbyoung Kang ,  Jinsu Kim ,  Seungwan Shin ,  Byoungwook Jang

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/544 ,  H01L23/3128 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01L2223/54433 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

Abstract: A semiconductor package includes a lower redistribution wiring layer having a first region and a second region adjacent the first region and including first redistribution wirings; a semiconductor chip on the first region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a sealing member on a side surface of the semiconductor chip and on the lower redistribution wiring layer; a plurality of vertical conductive structures penetrating the sealing member on the second region of the lower redistribution wiring layer and electrically connected to the first redistribution wirings; a marking pattern on the semiconductor chip; seed layer pads on respective end portions of the vertical conductive structures that are exposed by the sealing member at an upper surface thereof; and an upper redistribution wiring layer on the sealing member and the marking pattern and including second redistribution wirings.

公开(公告)号：US20240145444A1

公开(公告)日：2024-05-02

申请号：US18219396

申请日：2023-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiju Lee ,  Jinsu Kim ,  Hyunsuk Yang ,  Byoungwook Jang

IPC: H01L25/10 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438

Abstract: A semiconductor package is provided and includes: a first redistribution structure including a first redistribution pattern and a first redistribution insulating layer, wherein the first redistribution pattern includes a first redistribution via extending in a vertical direction within the first redistribution insulating layer; a second redistribution structure on the first redistribution structure and including a second redistribution pattern and a second redistribution insulating layer, wherein the second redistribution pattern includes a lower redistribution pad at a lower surface of the second redistribution insulating layer; a first semiconductor chip on the second redistribution structure; and a second semiconductor chip on the first semiconductor chip. An upper surface of the first redistribution insulating layer is in contact with the lower surface of the second redistribution insulating layer, and the the first redistribution via of the first redistribution structure is in contact with the lower redistribution pad of the second redistribution structure.