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    SEMICONDUCTOR PACKAGE WITH GLASS CORE SUBSTRATE AND METHOD OF FABRICATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR PACKAGE WITH GLASS CORE SUBSTRATE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20250022859A1

    公开(公告)日：2025-01-16

    申请号：US18427622

    申请日：2024-01-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghoon Kang

    IPC: H01L25/16 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/58 ,  H01L21/56

    Abstract: A semiconductor package includes a wiring substrate and a first semiconductor chip disposed on the wiring substrate. The wiring substrate includes a first core portion including glass and having a cavity that vertically penetrates the first core portion, first core vias that each vertically penetrate the first core portion, a passive device in the cavity of the first core portion, a buried material on the first core portion and the first core vias and filling the cavity and covering a top surface and outer lateral surfaces of the first core portion, and an upper buildup portion disposed on the buried material. The upper buildup portion includes a first dielectric pattern, and a first wiring pattern that penetrates the first dielectric pattern and the buried material and is coupled to the first core vias.

    SEMICONDUCTOR PACKAGE, ELECTRONIC APPARATUS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
    3.
    发明申请
    SEMICONDUCTOR PACKAGE, ELECTRONIC APPARATUS AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220293432A1

    公开(公告)日：2022-09-15

    申请号：US17827966

    申请日：2022-05-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghoon Kang

    IPC: H01L21/48 ,  H01L23/538 ,  H01L25/18 ,  H01L25/00 ,  H01L21/683

    Abstract: A semiconductor package includes an interposer having a separation layer on a rear surface of which a plurality of first recesses is arranged. A plurality of wiring structures is stacked on the separation layer alternately with a plurality of insulation interlayers. A plurality of semiconductor devices is arranged, side by side, on the interposer side and connected to a plurality of the wiring structures. A plurality of contact terminals on the rear surface of the separation layer is connected to the plurality of the wiring structures through the separation layer. A flatness deterioration of the interposer is minimized and the contact surface between the interposer and under fill resin is enlarged.

    Semiconductor package
    4.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US12100668B2

    公开(公告)日：2024-09-24

    申请号：US18496372

    申请日：2023-10-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghoon Kang

    IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L23/544 ,  H01L25/065

    CPC classification number: H01L23/544 ,  H01L23/3121 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517

    Abstract: A semiconductor package includes a first semiconductor chip; an encapsulant covering at least a portion of the first semiconductor chip; insulating layers provided on the encapsulant, each of the insulating layers being transparent or translucent; and wiring layers provided on the encapsulant, the wiring layers being partially covered by the insulating layers, wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, a color of the first region is different from a color of the second region, the second region surrounds the first region, and at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer.

    Semiconductor package
    6.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11837553B2

    公开(公告)日：2023-12-05

    申请号：US17405696

    申请日：2021-08-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghoon Kang

    IPC: H01L23/538 ,  H01L23/544 ,  H01L23/31 ,  H01L25/065 ,  H01L23/00

    CPC classification number: H01L23/544 ,  H01L23/3121 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517

    Abstract: A semiconductor package includes a first semiconductor chip; an encapsulant covering at least a portion of the first semiconductor chip; insulating layers provided on the encapsulant, each of the insulating layers being transparent or translucent; and wiring layers provided on the encapsulant, the wiring layers being partially covered by the insulating layers, wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, a color of the first region is different from a color of the second region, the second region surrounds the first region, and at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer.

    SEMICONDUCTOR PACKAGE
    7.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20220165634A1

    公开(公告)日：2022-05-26

    申请号：US17405696

    申请日：2021-08-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghoon Kang

    IPC: H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

    Abstract: A semiconductor package includes a first semiconductor chip; an encapsulant covering at least a portion of the first semiconductor chip; insulating layers provided on the encapsulant, each of the insulating layers being transparent or translucent; and wiring layers provided on the encapsulant, the wiring layers being partially covered by the insulating layers, wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, a color of the first region is different from a color of the second region, the second region surrounds the first region, and at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer.

    Semiconductor package having pad with regular and irregular depressions and protrusions and method of manufacturing the same
    8.
    发明授权
    Semiconductor package having pad with regular and irregular depressions and protrusions and method of manufacturing the same 有权

    公开(公告)号：US11929315B2

    公开(公告)日：2024-03-12

    申请号：US17527414

    申请日：2021-11-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghoon Kang

    IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00

    CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16227

    Abstract: A semiconductor package including a redistribution substrate having lower and upper surfaces, the redistribution substrate including a pad on the lower surface, the pad having a first surface and a second surface, and a redistribution layer electrically connected to the pad; a semiconductor chip on the upper surface of the redistribution substrate and electrically connected to the redistribution layer; an encapsulant encapsulating at least a portion of the semiconductor chip; and a protective layer on the lower surface of the redistribution substrate and having an opening exposing at least a portion of the first surface of the pad, wherein the portion of the first surface exposed through the opening includes a recess surface including regular depressions and protrusions and being depressed inwardly toward the second surface, and an edge surface including irregular depressions and protrusions and having a step difference with respect to the recess surface.

    METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR PACKAGE
    10.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230005843A1

    公开(公告)日：2023-01-05

    申请号：US17695478

    申请日：2022-03-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junghoon Kang

    IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48

    Abstract: A method includes attaching a first anisotropic conductive film including first conductive particles to a front surface of a substrate structure; compressing a first redistribution structure on the front surface of the substrate structure such that a first redistribution conductor of the first redistribution structure that is exposed is electrically connected by the first conductive particles to a connection terminal or a vertical connection conductor that is exposed from the substrate structure, attaching a second anisotropic conductive film including second conductive particles to a rear surface of the substrate structure; and compressing a second redistribution structure on the rear surface of the substrate structure such that a second redistribution conductor of the second redistribution structure that is exposed is electrically connected by the second conductive particles to the vertical connection conductor.

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