公开(公告)号：US20240258398A1

公开(公告)日：2024-08-01

申请号：US18381945

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junhyuk PARK ,  Jaejoon OH ,  Injun HWANG ,  Boram KIM ,  Jongseob KIM ,  Joonyong KIM

IPC: H01L29/47 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/475 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a p-type gallium nitride (GaN) layer on the barrier layer, an n-type interfacial layer on the p-type GaN layer, and a gate electrode on the n-type interfacial layer.

公开(公告)号：US20240243177A1

公开(公告)日：2024-07-18

申请号：US18347223

申请日：2023-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyong KIM ,  Jaejoon OH ,  Boram KIM ,  Jongseob KIM ,  Junhyuk PARK ,  Sunkyu HWANG ,  Injun HWANG

IPC: H01L29/20 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/2003 ,  H01L29/41766 ,  H01L29/66462 ,  H01L29/7786

Abstract: A method of manufacturing a semiconductor device according to various example embodiments includes forming a buffer layer and a first semiconductor layer on a substrate, forming a recess by etching the first semiconductor layer, sequentially forming a second semiconductor layer and a third semiconductor layer on the first semiconductor layer in which the recess is formed, and forming a source and a drain respectively in contact with both sides of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer.

公开(公告)号：US20230350472A1

公开(公告)日：2023-11-02

申请号：US18346394

申请日：2023-07-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ohhyuck KWON ,  Jaeyoung HUH ,  Daesuk KANG ,  Seunghoon KANG ,  Boram KIM ,  Hongki MOON ,  Yoonsun PARK ,  Kyungwoo LEE ,  Seungjoo LEE ,  Jonghoon LIM

IPC: G06F1/20 ,  H01L23/427 ,  G06F1/16

CPC classification number: G06F1/203 ,  H01L23/427 ,  G06F1/206 ,  G06F1/1637

Abstract: Disclosed is an electronic device including a housing including a first surface, a second surface facing away the first surface, and a third surface surrounding a space between the first surface and the second surface; a display exposed through the first surface; a battery disposed in the space; a heating source disposed between the battery and the third surface; and a thermal diffusion member disposed between the heating source and the battery. The thermal diffusion member includes a fluid; a first portion disposed adjacent to the heating source for receiving heat from the heating source; and at least one second portion extending from the first portion. The heat transferred from the heating source to the first portion is transferred from the first portion to the at least one second portion.

公开(公告)号：US20240274689A1

公开(公告)日：2024-08-15

申请号：US18436512

申请日：2024-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Injun HWANG ,  Jaejoon OH ,  Boram KIM ,  Sunkyu HWANG

IPC: H01L29/47 ,  H01L27/095 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/475 ,  H01L27/095 ,  H01L29/2003 ,  H01L29/7786

Abstract: A HEMT may include a channel layer including a 2DEG as a channel carrier, first and second electrodes separated on the channel layer, a first semiconductor layer on the channel layer between the first and second electrodes and having a greater band gap greater than the channel layer, a gate stack on the first semiconductor layer, and a gate electrode in ohmic contact with the gate stack. The gate stack may include a lower layer contacting the first semiconductor layer, a second semiconductor layer providing a Schottky barrier on the lower layer, and an upper layer on the second semiconductor layer. The upper layer may be doped with a p-type dopant and may have a lower band gap than the second semiconductor layer.

公开(公告)号：US20240096944A1

公开(公告)日：2024-03-21

申请号：US18133276

申请日：2023-04-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonyong KIM ,  Sunkyu HWANG ,  Boram KIM ,  Jongseob KIM ,  Junhyuk PARK ,  Jaejoon OH ,  Injun HWANG

IPC: H01L29/06 ,  H01L21/3065 ,  H01L23/473 ,  H01L29/66 ,  H10N39/00

CPC classification number: H01L29/0657 ,  H01L21/3065 ,  H01L23/473 ,  H01L29/66462 ,  H10N39/00 ,  H01L29/7786

Abstract: Provided are a power device and a manufacturing method thereof. A power device includes a compound semiconductor layer epitaxially grown on a substrate, a gate formed on the compound semiconductor layer, a source and a drain provided on either side of the gate, a passivation layer provided to cover the source, drain, and gate, and a cooling space region provided to form a cooling path inside the substrate. The cooling space region may be formed to a predetermined depth from the surface of the substrate and include an enlargement region having a width increasing according to a depth from the surface of the substrate. The width of an inlet of the cooling space region is less than a maximum width of the enlargement region, and the passivation layer and the compound semiconductor layer are provided to open the cooling space region.

公开(公告)号：US20210399120A1

公开(公告)日：2021-12-23

申请号：US17098896

申请日：2020-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunkyu HWANG ,  Joonyong KIM ,  Jongseob KIM ,  Junhyuk PARK ,  Boram KIM ,  Younghwan PARK ,  Dongchul SHIN ,  Jaejoon OH ,  Soogine CHONG ,  Injun HWANG

IPC: H01L29/778 ,  H01L29/66

Abstract: Provided is a high electron mobility transistor including: a channel layer comprising a 2-dimensional electron gas (2DEG); a barrier layer on the channel layer and comprising first regions and a second region, the first regions configured to induce the 2DEG of a first density in portions of the channel layer and the second region configured to induce the 2DEG of a second density different from the first density in other portions of the channel layer; source and drain electrodes on the barrier layer; a depletion formation layer formed on the barrier layer between the source and drain electrodes to form a depletion region in the 2DEG; and a gate electrode on the barrier layer. The first regions may include a first edge region and a second edge region corresponding to both ends of a surface of the gate electrode facing the channel layer.

公开(公告)号：US20200220572A1

公开(公告)日：2020-07-09

申请号：US16733975

申请日：2020-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ohhyuck KWON ,  Jaeyoung HUH ,  Daesuk KANG ,  Boram KIM ,  Jonghoon LIM ,  Sungchul PARK

IPC: H04B1/44 ,  H04B1/00 ,  H01Q3/24 ,  H01Q21/00 ,  H04M1/02

Abstract: Methods and devices for antenna switching are provided. A wireless signal is transmitted and received through a specific antenna module among a plurality of antenna modules. Status information about each of one or more other antenna modules among the plurality of antenna modules is acquired, when a temperature of the specific antenna module exceeds a predetermined value. The temperature of the specific antenna module is measured through a respective sensor module of a plurality of sensor modules. Each sensor module of the plurality of sensor modules is contained in or disposed adjacent to a respective antenna module of the plurality of antenna modules. The specific antenna module is switched to an antenna module selected from among the one or more other antenna modules, based on the acquired status information.

公开(公告)号：US20250169096A1

公开(公告)日：2025-05-22

申请号：US18671507

申请日：2024-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjun LEE ,  Boram KIM ,  JONGSEOB KIM ,  JONGUK SEO ,  JUNGSEUNG YANG ,  JAEJOON OH ,  YONGSEOK CHOI

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device according to an embodiment includes: a channel layer; a barrier layer above the channel layer and including a material having an energy band gap different from an energy band gap of the channel layer; a gate electrode above the barrier layer; a gate semiconductor layer between the barrier layer and the gate electrode; a source electrode and a drain electrode that are at both sides of the gate electrode and covering side surfaces of the channel layer and the barrier layer; and a superlattice layer between the barrier layer and the gate semiconductor layer, the superlattice layer including at least one first layer including AlGaN and at least one second layer including GaN, wherein the at least one first layer and the at least one second layer are alternately stacked.

公开(公告)号：US20240113184A1

公开(公告)日：2024-04-04

申请号：US18193859

申请日：2023-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyuk PARK ,  Jaejoon OH ,  Sunkyu HWANG ,  Boram KIM ,  Jongseob KIM ,  Joonyong KIM ,  Injun HWANG

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/42316 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device may include a barrier layer on a channel layer, a gate electrode on the barrier layer, a gate semiconductor layer between the barrier layer and the gate electrode, and a source and a drain spaced apart from each other on the channel layer. The barrier layer may have a greater energy band gap than the channel layer. The gate semiconductor layer may include a first surface contacting the barrier layer and a second surface contacting the gate electrode, and a sidewall connecting the first surface with the second surface. An area of the second surface of the gate semiconductor layer may be narrower than an area of the first surface. The sidewall of the gate semiconductor layer may include a plurality of surfaces having different slopes.

公开(公告)号：US20250159844A1

公开(公告)日：2025-05-15

申请号：US18946026

申请日：2024-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boram KIM ,  Ohhyuck KWON ,  Youngjin KIM ,  Min PARK ,  Jungoh SUNG ,  Changjong SON ,  Yoonhee CHANG ,  Jinhwan JUNG ,  Jieun HWANG ,  Jihyeon SON ,  Jeonggen YOON

IPC: H05K7/20 ,  H05K9/00

Abstract: The disclosure relates to an electronic device. An electronic device according to an embodiment of the disclosure may comprise: a printed circuit board, a first electronic component mounted on the printed circuit board, a second electronic component mounted in a first area of a surface of the first electronic component, and a thermoresponsive heat dissipation member comprising a heat dissipation material and contacting a second area of the surface of the first electronic component and a top surface of the second electronic component. The heat dissipation member is configured to be in a solid phase and is configured to be softened based on a temperature of the heat dissipation member.