HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20250056827A1

    公开(公告)日:2025-02-13

    申请号:US18928499

    申请日:2024-10-28

    Abstract: A high electron mobility transistor and a method of manufacturing the same are disclosed. The high electron mobility transistor includes a channel layer, a channel supplying layer causing generation of a two-dimensional electron gas (2DEG) in the channel layer, a source electrode and a drain electrode provided on respective sides of the channel supplying layer, a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG, a gate electrode provided on a portion of the depletion forming layer, and a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer. The current limiting layer limits a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode.

    HIGH ELECTRON MOBILITY TRANSISTOR

    公开(公告)号:US20230019799A1

    公开(公告)日:2023-01-19

    申请号:US17679288

    申请日:2022-02-24

    Abstract: A high electron mobility transistor includes a channel layer; a barrier layer on the channel layer and having an energy bandgap greater than an energy bandgap of the channel layer; a gate structure on the barrier layer; a source electrode and a drain electrode spaced apart from each other on the barrier layer with the gate structure therebetween; a field plate electrically connected to the source electrode and extending above the gate structure; and a field dispersion layer in contact with the barrier layer and the drain electrode. The field dispersion layer may extend toward the gate structure.

    POWER DEVICE AND METHOD OF MANUFACTURING THE SAME

    公开(公告)号:US20220320327A1

    公开(公告)日:2022-10-06

    申请号:US17398407

    申请日:2021-08-10

    Abstract: Provided are a power device and a method of manufacturing the same. The power device may include a channel layer; a source and a drain at respective sides of the channel layer; a gate on the channel layer between the source and the drain; a passivation layer covering the source, the drain, and the gate; and a plurality of field plates in the passivation layer. The plurality of field plates may have different thicknesses. The plurality of field plates may have different widths, different pattern shapes, or both different widths and different pattern shapes.

    SEMICONDUCTOR DEVICE PACKAGE
    10.
    发明公开

    公开(公告)号:US20240055330A1

    公开(公告)日:2024-02-15

    申请号:US18495697

    申请日:2023-10-26

    Abstract: A semiconductor device package includes a lead frame, a semiconductor device including a first face connected to the lead frame, a second face that faces the first face, a gate pad, a drain pad, and a source pad, the gate pad exposed on the second face of the semiconductor, the drain pad exposed on the second face of the second face, and the source pad exposed on the second face, a gate clip connected to the gate pad, a drain clip connected to the drain pad, a source clip connected to the source pad, the source clip connected to the lead frame, and a molding that seals the lead frame, the semiconductor device, the source clip, the drain clip, and the gate clip.

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