公开(公告)号：US20250056827A1

公开(公告)日：2025-02-13

申请号：US18928499

申请日：2024-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaejoon OH ,  Jongseob KIM

IPC: H01L29/778 ,  H01L21/285 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

Abstract: A high electron mobility transistor and a method of manufacturing the same are disclosed. The high electron mobility transistor includes a channel layer, a channel supplying layer causing generation of a two-dimensional electron gas (2DEG) in the channel layer, a source electrode and a drain electrode provided on respective sides of the channel supplying layer, a depletion forming layer provided on the channel supplying layer to form a depletion region in the 2DEG, a gate electrode provided on a portion of the depletion forming layer, and a current limiting layer provided to contact the gate electrode on another portion of the depletion forming layer. The current limiting layer limits a current flow from the gate electrode to the depletion forming layer according to a voltage applied to the gate electrode.

公开(公告)号：US20240113184A1

公开(公告)日：2024-04-04

申请号：US18193859

申请日：2023-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyuk PARK ,  Jaejoon OH ,  Sunkyu HWANG ,  Boram KIM ,  Jongseob KIM ,  Joonyong KIM ,  Injun HWANG

IPC: H01L29/423 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/42316 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device may include a barrier layer on a channel layer, a gate electrode on the barrier layer, a gate semiconductor layer between the barrier layer and the gate electrode, and a source and a drain spaced apart from each other on the channel layer. The barrier layer may have a greater energy band gap than the channel layer. The gate semiconductor layer may include a first surface contacting the barrier layer and a second surface contacting the gate electrode, and a sidewall connecting the first surface with the second surface. An area of the second surface of the gate semiconductor layer may be narrower than an area of the first surface. The sidewall of the gate semiconductor layer may include a plurality of surfaces having different slopes.

公开(公告)号：US20220148948A1

公开(公告)日：2022-05-12

申请号：US17227850

申请日：2021-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan PARK ,  Jongseob KIM ,  Jaejoon OH ,  Soogine CHONG ,  Sunkyu HWANG

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/367 ,  H01L29/20

Abstract: Provided are a semiconductor device package and/or a method of fabricating the semiconductor device package. The semiconductor device package may include a semiconductor device including a plurality of electrode pads on an upper surface of the semiconductor device, a lead frame including a plurality of conductive members bonded to the plurality of electrode pads, and a mold between the plurality of conductive members.

公开(公告)号：US20240213327A1

公开(公告)日：2024-06-27

申请号：US18485740

申请日：2023-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Boram KIM ,  Jaejoon OH ,  Jongseob KIM

IPC: H01L29/15 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/155 ,  H01L29/2003 ,  H01L29/7786

Abstract: Provided are a superlattice buffer structure and a semiconductor device having the superlattice buffer structure. The superlattice buffer structure includes a plurality of superlattice blocks, and each of the plurality of superlattice blocks has a structure in which a first layer including Al(1−x)GaxN (0≤x≤1) and a second layer including Al(1−y)GayN (0≤y≤1, x>y) are alternately stacked on each other.

公开(公告)号：US20230019799A1

公开(公告)日：2023-01-19

申请号：US17679288

申请日：2022-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan PARK ,  Woochul JEON ,  Jongseob KIM

IPC: H01L29/778 ,  H01L29/40

Abstract: A high electron mobility transistor includes a channel layer; a barrier layer on the channel layer and having an energy bandgap greater than an energy bandgap of the channel layer; a gate structure on the barrier layer; a source electrode and a drain electrode spaced apart from each other on the barrier layer with the gate structure therebetween; a field plate electrically connected to the source electrode and extending above the gate structure; and a field dispersion layer in contact with the barrier layer and the drain electrode. The field dispersion layer may extend toward the gate structure.

公开(公告)号：US20220320327A1

公开(公告)日：2022-10-06

申请号：US17398407

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyong KIM ,  Sunkyu HWANG ,  Jongseob KIM ,  Junhyuk PARK

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/66 ,  H01L29/20

Abstract: Provided are a power device and a method of manufacturing the same. The power device may include a channel layer; a source and a drain at respective sides of the channel layer; a gate on the channel layer between the source and the drain; a passivation layer covering the source, the drain, and the gate; and a plurality of field plates in the passivation layer. The plurality of field plates may have different thicknesses. The plurality of field plates may have different widths, different pattern shapes, or both different widths and different pattern shapes.

公开(公告)号：US20220013659A1

公开(公告)日：2022-01-13

申请号：US17082478

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Injun HWANG ,  Jaejoon OH ,  Soogine CHONG ,  Jongseob KIM ,  Joonyong KIM ,  Junhyuk PARK ,  Sunkyu HWANG

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/40 ,  H01L29/66

Abstract: A high electron mobility transistor (HEMT) includes a channel layer comprising a group III-V compound semiconductor; a barrier layer comprising the group III-V compound semiconductor on the channel layer; a gate electrode on the barrier layer; a source electrode over gate electrode; a drain electrode spaced apart from the source electrode; and a metal wiring layer. A same layer of the metal wiring layer includes a gate wiring connected to the gate electrode, a source field plate connected to the source electrode, and a drain field plate connected to the drain electrode.

公开(公告)号：US20210336045A1

公开(公告)日：2021-10-28

申请号：US17016890

申请日：2020-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaejoon OH ,  Jongseob KIM

IPC: H01L29/778 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66

Abstract: Provided are a high electron mobility transistor and a method of manufacturing the high electron mobility transistor. The high electron mobility transistor includes a gate electrode provided on a depletion forming layer. The gate electrode includes a first gate electrode configured to form an ohmic contact with the depletion forming layer, and a second gate electrode configured to form a Schottky contact with the depletion forming layer.

公开(公告)号：US20240204092A1

公开(公告)日：2024-06-20

申请号：US18321284

申请日：2023-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhyuk PARK ,  Jaejoon OH ,  Sunkyu HWANG ,  Boram KIM ,  Jongseob KIM ,  Joonyong KIM

IPC: H01L29/778 ,  H01L23/31 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/66462

Abstract: A semiconductor device includes a channel layer, a lower barrier layer on the channel layer and including first impurities, an upper barrier layer arranged on the lower barrier layer and including second impurities having a concentration greater than a concentration of the first impurities, a gate electrode on the upper barrier layer, a gate semiconductor layer between the upper barrier layer and the gate electrode, and a source and a drain that are on the channel layer and are spaced apart from each other.

公开(公告)号：US20240055330A1

公开(公告)日：2024-02-15

申请号：US18495697

申请日：2023-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan PARK ,  Jongseob KIM ,  Jaejoon OH ,  Soogine CHONG ,  Sunkyu HWANG

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49562 ,  H01L21/4825 ,  H01L23/4951 ,  H01L23/49524 ,  H01L23/49568

Abstract: A semiconductor device package includes a lead frame, a semiconductor device including a first face connected to the lead frame, a second face that faces the first face, a gate pad, a drain pad, and a source pad, the gate pad exposed on the second face of the semiconductor, the drain pad exposed on the second face of the second face, and the source pad exposed on the second face, a gate clip connected to the gate pad, a drain clip connected to the drain pad, a source clip connected to the source pad, the source clip connected to the lead frame, and a molding that seals the lead frame, the semiconductor device, the source clip, the drain clip, and the gate clip.