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    Display panel
    1.
    发明授权
    Display panel 有权

    公开(公告)号：US12027097B2

    公开(公告)日：2024-07-02

    申请号：US18135212

    申请日：2023-04-17

    Applicant: Samsung Display Co., Ltd.

    Inventor： Jung Hwan Hwang ,  Beom Jun Kim ,  Seong Yeol Syn ,  Bong-Jun Lee ,  You Mee Hyun

    IPC: G09G3/20 ,  G09G3/36 ,  G11C19/28

    CPC classification number: G09G3/2092 ,  G09G3/3648 ,  G09G3/3677 ,  G11C19/28 ,  G09G2300/0809 ,  G09G2310/0286

    Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

    Liquid crystal display having contact holes adjacently disposed in thin film transistor forming region
    3.
    发明授权
    Liquid crystal display having contact holes adjacently disposed in thin film transistor forming region 有权
    具有相邻设置在薄膜晶体管形成区域中的接触孔的液晶显示器

    公开(公告)号：US09568790B2

    公开(公告)日：2017-02-14

    申请号：US14476570

    申请日：2014-09-03

    Applicant: Samsung Display Co., Ltd.

    Inventor： Yun Heo ,  Bong-Jun Lee ,  Dong Wuuk Seo ,  Jong Woong Chang

    IPC: G02F1/136 ,  G02F1/1362 ,  G02F1/1337

    CPC classification number: G02F1/136227 ,  G02F1/133707 ,  G02F2201/40

    Abstract: A liquid crystal display includes: a first substrate; a gate line and a common voltage line that are on the first substrate; a gate insulating layer on the gate line and the common voltage line; a semiconductor layer on the gate insulating layer; a data line and a drain electrode that are on the semiconductor layer; a pixel electrode on the data line and the drain electrode; a passivation layer on the pixel electrode; a common electrode on the passivation layer; a second substrate; and a liquid crystal layer interposed between the first and second substrates. The pixel electrode contacts the drain electrode via a first contact hole, the common electrode contacts the common voltage line via a second contact hole in the gate insulating layer and the passivation layer, and the first and second contact holes are adjacently disposed in a thin film transistor forming region.

    Abstract translation: 液晶显示器包括：第一基板; 位于第一基板上的栅极线和公共电压线; 栅极线和公共电压线上的栅极绝缘层; 栅极绝缘层上的半导体层; 数据线和漏电极，位于半导体层上; 数据线和漏电极上的像素电极; 像素电极上的钝化层; 钝化层上的公共电极; 第二基板; 以及插入在第一和第二基板之间的液晶层。 像素电极经由第一接触孔接触漏极，公共电极经由栅极绝缘层和钝化层中的第二接触孔接触公共电压线，并且第一和第二接触孔相邻地设置在薄膜 晶体管形成区域。

    LIQUID CRYSTAL DISPLAY
    4.
    发明申请
    LIQUID CRYSTAL DISPLAY 审中-公开
    液晶显示器

    公开(公告)号：US20160282685A1

    公开(公告)日：2016-09-29

    申请号：US15180259

    申请日：2016-06-13

    Applicant: Samsung Display Co., Ltd.

    Inventor： Duk-Sung Kim ,  Bong-Jun Lee ,  Sung Man Kim ,  Seul Ki Kim ,  Jin Yun Kim ,  Dong Wuuk Seo ,  Min Hee Son

    IPC: G02F1/1343 ,  H01L29/786 ,  G02F1/1362 ,  H01L27/12 ,  G02F1/1333 ,  G02F1/1368

    CPC classification number: G02F1/134309 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/1343 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134318 ,  G02F2001/134372 ,  G02F2001/136272 ,  G02F2201/121 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869

    Abstract: A display, includes: a substrate; first signal lines (FSLs) disposed on the substrate and extending in substantially a first direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the first direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

    Abstract translation: 一种显示器，包括：基板; 第一信号线（FSL），其设置在基板上并且基本上沿第一方向延伸; 设置在FSL上的栅极绝缘层（GIL）; 设置在GIL上的第一电极; 连接到FSL的FSL并且包括GIL和第一电极的薄膜晶体管（TFT）; 基本上沿第一方向延伸的像素电极（PE），连接到TFT，并被配置为从TFT接收数据电压; 与PE的至少一部分重叠的公共电极（CE）; 以及设置在PE和CE之间的第一绝缘层。 PE和CE中的一个具有平面形状，另一个包括与平面形状重叠并且基本上平行于FSL延伸的分支电极。 CE的至少一部分与FSL的至少一部分重叠。

    DISPLAY DEVICE
    7.
    发明申请
    DISPLAY DEVICE 有权
    显示设备

    公开(公告)号：US20140209910A1

    公开(公告)日：2014-07-31

    申请号：US13940405

    申请日：2013-07-12

    Applicant: Samsung Display Co., Ltd.

    Inventor： Hong-Kyu KIM ,  Bong-Jun Lee ,  Ju Hee Lee ,  Sun-Kwun Son ,  Jae Yoon Jung ,  Seung Han Jo

    IPC: H01L27/12

    CPC classification number: H01L27/124 ,  G02F1/134309 ,  G02F1/136286 ,  H01L23/48 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522

    Abstract: A display device includes a signal line disposed on a substrate. A signal input line is disposed on the substrate and connected to a driver. A first insulating layer is disposed on the signal line. A second insulating layer is disposed on the signal input line and the first insulating layer. First contact holes penetrate the first insulating layer and the second insulating layer and expose a portion of the signal line. Second contact holes penetrate the second insulating layer and expose a portion of the signal input line. A connecting member connects the signal line and the signal input line through the first and the second contact holes and is disposed on the second insulating layer. The first and the second contact holes are alternately arranged in the second insulating layer.

    Abstract translation: 显示装置包括设置在基板上的信号线。 信号输入线设置在基板上并连接到驱动器。 第一绝缘层设置在信号线上。 第二绝缘层设置在信号输入线和第一绝缘层上。 第一接触孔穿透第一绝缘层和第二绝缘层，并暴露信号线的一部分。 第二接触孔穿透第二绝缘层并暴露信号输入线的一部分。 连接构件通过第一和第二接触孔连接信号线和信号输入线，并且设置在第二绝缘层上。 第一和第二接触孔交替布置在第二绝缘层中。

    Display panel
    8.
    发明授权
    Display panel 有权

    公开(公告)号：US11631359B2

    公开(公告)日：2023-04-18

    申请号：US17209068

    申请日：2021-03-22

    Applicant: Samsung Display Co., Ltd.

    Inventor： Jung Hwan Hwang ,  Beom Jun Kim ,  Seong Yeol Syn ,  Bong-Jun Lee ,  You Mee Hyun

    IPC: G09G3/20 ,  G09G3/36 ,  G11C19/28

    Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

    Display panel
    10.
    发明授权
    Display panel 有权
    显示面板

    公开(公告)号：US09589519B2

    公开(公告)日：2017-03-07

    申请号：US14203272

    申请日：2014-03-10

    Applicant: Samsung Display Co., Ltd.

    Inventor： Jung Hwan Hwang ,  Beom Jun Kim ,  Seong Yeol Syn ,  Bong-Jun Lee ,  You Mee Hyun

    IPC: G09G3/36 ,  G11C19/28

    CPC classification number: G09G3/2092 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0286 ,  G11C19/28

    Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

    Abstract translation: 提供显示面板。 显示面板包括包括栅线和数据线的显示区域，以及连接到栅极线的端子的栅极驱动器。 栅极驱动器包括集成在衬底上的多个级，并且每个级包括逆变器单元，输出单元和Q结点稳定单元。 输出单元包括第一晶体管和第一电容器，其中第一晶体管包括用于接收时钟信号的输入端子，连接到节点Q的控制端子和连接到栅极电压输出端子的输出端子以输出栅极 电压。 当输出单元输出栅极导通电压时，Q节点稳定单元中的晶体管的Vgs电压具有等于或小于0V的值。

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