Abstract:
A display, includes: a substrate; first signal lines (FSLs) at least partially recessed in the substrate and extending in substantially a direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.
Abstract:
A liquid crystal display includes: a first substrate; a gate line and a common voltage line that are on the first substrate; a gate insulating layer on the gate line and the common voltage line; a semiconductor layer on the gate insulating layer; a data line and a drain electrode that are on the semiconductor layer; a pixel electrode on the data line and the drain electrode; a passivation layer on the pixel electrode; a common electrode on the passivation layer; a second substrate; and a liquid crystal layer interposed between the first and second substrates. The pixel electrode contacts the drain electrode via a first contact hole, the common electrode contacts the common voltage line via a second contact hole in the gate insulating layer and the passivation layer, and the first and second contact holes are adjacently disposed in a thin film transistor forming region.
Abstract:
A display, includes: a substrate; first signal lines (FSLs) disposed on the substrate and extending in substantially a first direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the first direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.
Abstract:
A display, includes: a substrate; first signal lines (FSLs) at least partially recessed in the substrate and extending in substantially a direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.
Abstract:
A display, includes: a substrate; first signal lines (FSLs) disposed on the substrate and extending in substantially a first direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the first direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.
Abstract:
A display, includes: a substrate; first signal lines (FSLs) disposed on the substrate and extending in substantially a first direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the first direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.