公开(公告)号：US12014924B2

公开(公告)日：2024-06-18

申请号：US17258967

申请日：2019-06-14

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Kenji Kanbara ,  Hironori Itoh ,  Tsutomu Hori

IPC: H01L29/36 ,  C30B29/36 ,  H01L21/02 ,  H01L21/04 ,  H01L21/78 ,  H01L29/16 ,  H01L29/34 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/02529 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/046 ,  H01L21/78 ,  H01L29/1608 ,  H01L29/34 ,  H01L29/66068 ,  H01L29/7802

Abstract: When a value obtained by dividing the number of the one or more second regions by a total of the number of the one or more first regions and the number of the one or more second regions is defined as a first defect free area ratio, a value obtained by dividing the number of the one or more fourth regions by a total of the number of the one or more third regions and the number of the one or more fourth regions is defined as a second defect free area ratio, and a value obtained by dividing the number of the one or more macroscopic defects by an area of the central region is defined as X cm−2, A is smaller than B, B is less than or equal to 4, X is more than 0 and less than 4, and a Formula 1 is satisfied.

公开(公告)号：US10526699B2

公开(公告)日：2020-01-07

申请号：US16340007

申请日：2018-07-20

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Kenji Kanbara ,  Takaya Miyase ,  Tsubasa Honke

IPC: C23C16/42 ,  C30B25/02 ,  H01L29/16 ,  H01L21/205 ,  C30B29/36 ,  H01L21/20 ,  H01L29/12 ,  H01L29/78

Abstract: A silicon carbide epitaxial film has a plurality of arc-shaped or annular basal plane dislocations and a plurality of threading dislocations. The plurality of threading dislocations have a first threading dislocation which is surrounded by the plurality of basal plane dislocations and a second threading dislocation which is not surrounded by the plurality of basal plane dislocations, when viewed from a direction perpendicular to a main surface. The plurality of basal plane dislocations and the first threading dislocation constitute an annular defect. An area density of the plurality of threading dislocations in the main surface is more than or equal to 50 cm−2. A value obtained by dividing an area density of the annular defect when viewed from the direction perpendicular to the main surface by the area density of the plurality of threading dislocations in the main surface is more than or equal to 0.00002 and less than or equal to 0.004.

公开(公告)号：US20180005816A1

公开(公告)日：2018-01-04

申请号：US15542821

申请日：2015-06-23

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Kenji Kanbara ,  Keiji Wada ,  Tsubasa Honke

IPC: H01L21/02 ,  C30B29/36 ,  H01L29/16 ,  C30B25/20 ,  H01L29/36 ,  H01L29/34

CPC classification number: H01L21/0243 ,  C23C16/325 ,  C23C16/4585 ,  C30B25/20 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/0262 ,  H01L29/1608 ,  H01L29/34 ,  H01L29/36

Abstract: A semiconductor laminate includes a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, and an epitaxial layer composed of silicon carbide disposed on the first main surface. The second main surface has an average value of roughness Ra of 0.1 μm or more and 1 μm or less with a standard deviation of 25% or less of the average value.

公开(公告)号：US20160233080A1

公开(公告)日：2016-08-11

申请号：US15024110

申请日：2014-08-11

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： So Tanaka ,  Kyoko Okita ,  Taro Nishiguchi ,  Ryosuke Kubota ,  Kenji Kanbara

IPC: H01L21/02 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L21/02021 ,  C30B23/00 ,  C30B25/186 ,  C30B29/36 ,  C30B33/00 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1608

Abstract: A silicon carbide semiconductor substrate includes a first main surface and a second main surface opposite to the first main surface. The first main surface has a maximum diameter of more than 100 mm, and the silicon carbide semiconductor substrate has a thickness of not more than 700 μm. A dislocation density is not more than 500/mm2 at an arbitrary region having an area of 1 mm2 in a region within 5 mm from an outer circumferential end portion of the first main surface toward a center of the first main surface. Accordingly, there is provided a silicon carbide semiconductor substrate allowing for suppression of generation of cracks.

Abstract translation: 碳化硅半导体衬底包括与第一主表面相对的第一主表面和第二主表面。 第一主表面的最大直径大于100mm，碳化硅半导体衬底的厚度不大于700μm。 在距离第一主表面的外周端部朝向第一主表面的中心的5mm以内的区域中，在面积为1mm2的任意区域，位错密度不大于500 / mm2。 因此，提供了能够抑制裂纹的产生的碳化硅半导体基板。

公开(公告)号：US20190019868A1

公开(公告)日：2019-01-17

申请号：US15750606

申请日：2016-08-04

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Keiji Wada ,  Hironori Itoh ,  Takemi Terao ,  Kenji Kanbara ,  Taro Nishiguchi

IPC: H01L29/16 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  C30B25/20 ,  H01L29/04

CPC classification number: H01L29/1608 ,  C23C16/325 ,  C30B25/20 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/0262 ,  H01L29/045 ,  H01L29/66068 ,  H01L29/7801

Abstract: A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. The silicon carbide single crystal substrate has a first main surface. The silicon carbide layer is on the first main surface. The silicon carbide layer includes a second main surface opposite to a surface thereof in contact with the silicon carbide single crystal substrate. The second main surface has a maximum diameter of more than or equal to 100 mm. The second main surface includes an outer peripheral region which is within 3 mm from an outer edge of the second main surface, and a central region surrounded by the outer peripheral region. The central region has a haze of less than or equal to 75 ppm.

公开(公告)号：US09966249B2

公开(公告)日：2018-05-08

申请号：US15024110

申请日：2014-08-11

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： So Tanaka ,  Kyoko Okita ,  Taro Nishiguchi ,  Ryosuke Kubota ,  Kenji Kanbara

IPC: C30B25/18 ,  C30B33/00 ,  C30B29/36 ,  H01L29/04 ,  H01L29/16 ,  H01L21/02 ,  C30B23/00 ,  H01L29/06

CPC classification number: H01L21/02021 ,  C30B23/00 ,  C30B25/186 ,  C30B29/36 ,  C30B33/00 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/1608

Abstract: A silicon carbide semiconductor substrate includes a first main surface and a second main surface opposite to the first main surface. The first main surface has a maximum diameter of more than 100 mm, and the silicon carbide semiconductor substrate has a thickness of not more than 700 μm. A dislocation density is not more than 500/mm2 at an arbitrary region having an area of 1 mm2 in a region within 5 mm from an outer circumferential end portion of the first main surface toward a center of the first main surface. Accordingly, there is provided a silicon carbide semiconductor substrate allowing for suppression of generation of cracks.

公开(公告)号：US20140061670A1

公开(公告)日：2014-03-06

申请号：US13947765

申请日：2013-07-22

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Keiji Wada ,  Kenji Kanbara

IPC: H01L29/872 ,  H01L29/66

CPC classification number: H01L29/872 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/47 ,  H01L29/475 ,  H01L29/66022 ,  H01L29/6603 ,  H01L29/6606 ,  H01L29/66143 ,  H01L29/66212

Abstract: A wide gap semiconductor device has a substrate and a Schottky electrode. The substrate is made of a wide gap semiconductor material and has a first conductivity type. The Schottky electrode is arranged on the substrate to be in contact therewith and is made of a single material. The Schottky electrode includes a first region having a first barrier height and a second region having a second barrier height higher than the first barrier height. The second region includes an outer peripheral portion of the Schottky electrode. Thus, a wide gap semiconductor device capable of achieving less leakage current and a method for manufacturing the same can be provided.

Abstract translation: 宽间隙半导体器件具有衬底和肖特基电极。 衬底由宽间隙半导体材料制成并具有第一导电类型。 肖特基电极布置在基板上以与其接触并由单一材料制成。 肖特基电极包括具有第一势垒高度的第一区域和具有高于第一势垒高度的第二势垒高度的第二区域。 第二区域包括肖特基电极的外周部分。 因此，可以提供能够实现较少漏电流的宽间隙半导体器件及其制造方法。

公开(公告)号：US10396163B2

公开(公告)日：2019-08-27

申请号：US15750606

申请日：2016-08-04

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Keiji Wada ,  Hironori Itoh ,  Takemi Terao ,  Kenji Kanbara ,  Taro Nishiguchi

IPC: H01L29/15 ,  H01L29/16 ,  C30B25/20 ,  C30B29/36 ,  H01L21/02 ,  C23C16/32 ,  H01L29/04 ,  H01L29/66 ,  H01L29/78

Abstract: A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. The silicon carbide single crystal substrate has a first main surface. The silicon carbide layer is on the first main surface. The silicon carbide layer includes a second main surface opposite to a surface thereof in contact with the silicon carbide single crystal substrate. The second main surface has a maximum diameter of more than or equal to 100 mm. The second main surface includes an outer peripheral region which is within 3 mm from an outer edge of the second main surface, and a central region surrounded by the outer peripheral region. The central region has a haze of less than or equal to 75 ppm.

公开(公告)号：US09559217B2

公开(公告)日：2017-01-31

申请号：US14892163

申请日：2014-04-02

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： Keiji Wada ,  Kenji Kanbara

IPC: H01L29/87 ,  H01L29/872 ,  H01L29/36 ,  H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/47

CPC classification number: H01L29/872 ,  H01L21/046 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/47 ,  H01L29/6606

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer, an insulating layer, a Schottky electrode, and a reaction region. The silicon carbide layer includes a p type region in contact with a first main surface and an n type region in contact with the p type region and the first main surface. The insulating layer has a third main surface, a fourth main surface, and a side wall surface connecting the third main surface and the fourth main surface, and is in contact with the first main surface at the fourth main surface. The Schottky electrode is in contact with the first main surface and the side wall surface. The reaction region is in contact with the insulating layer, the Schottky electrode, and the p type region. The reaction region contains an element constituting the Schottky electrode, an element constituting the insulating layer, silicon, and carbon.

Abstract translation: 碳化硅半导体器件包括碳化硅层，绝缘层，肖特基电极和反应区域。 碳化硅层包括与第一主表面接触的p型区域和与p型区域和第一主表面接触的n型区域。 绝缘层具有第三主表面，第四主表面和连接第三主表面和第四主表面的侧壁表面，并且在第四主表面处与第一主表面接触。 肖特基电极与第一主表面和侧壁表面接触。 反应区域与绝缘层，肖特基电极和p型区域接触。 反应区域包含构成肖特基电极的元件，构成绝缘层的元素，硅和碳。

公开(公告)号：US20160093749A1

公开(公告)日：2016-03-31

申请号：US14892163

申请日：2014-04-02

Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.

Inventor： Keiji Wada ,  Kenji Kanbara

IPC: H01L29/872 ,  H01L29/47 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/872 ,  H01L21/046 ,  H01L21/0495 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/47 ,  H01L29/6606

Abstract: A silicon carbide semiconductor device includes a silicon carbide layer, an insulating layer, a Schottky electrode, and a reaction region. The silicon carbide layer includes a p type region in contact with a first main surface and an n type region in contact with the p type region and the first main surface. The insulating layer has a third main surface, a fourth main surface, and a side wall surface connecting the third main surface and the fourth main surface, and is in contact with the first main surface at the fourth main surface. The Schottky electrode is in contact with the first main surface and the side wall surface. The reaction region is in contact with the insulating layer, the Schottky electrode, and the p type region. The reaction region contains an element constituting the Schottky electrode, an element constituting the insulating layer, silicon, and carbon.

Abstract translation: 碳化硅半导体器件包括碳化硅层，绝缘层，肖特基电极和反应区域。 碳化硅层包括与第一主表面接触的p型区域和与p型区域和第一主表面接触的n型区域。 绝缘层具有第三主表面，第四主表面和连接第三主表面和第四主表面的侧壁表面，并且在第四主表面处与第一主表面接触。 肖特基电极与第一主表面和侧壁表面接触。 反应区域与绝缘层，肖特基电极和p型区域接触。 反应区域包含构成肖特基电极的元件，构成绝缘层的元素，硅和碳。