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公开(公告)号：US20190081650A1
公开(公告)日：2019-03-14
申请号：US16191218
申请日：2018-11-14
CPC分类号： H04B1/0475 , H03F1/223 , H03F1/3205 , H03F3/193 , H03F3/211 , H03F3/24 , H03F3/245 , H03F2200/111 , H03F2200/294 , H03F2200/333 , H03F2200/451 , H03F2200/75 , H04B2001/0408
摘要： A power amplifier circuit includes a transistor having a first terminal that is configured to receive an input signal, a second terminal electrically coupled to ground, and a third terminal configured to transmit a combined amplified signal. The power amplifier circuit further includes a combining signal input path electrically coupled to the second terminal and configured to receive a combining signal and provide the combining signal to the second terminal of the transistor to generate, at least in part, the combined amplified signal.
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公开(公告)号：US20180248523A1
公开(公告)日：2018-08-30
申请号：US15965551
申请日：2018-04-27
CPC分类号： H03F1/32 , H03F1/0205 , H03F1/22 , H03F1/56 , H03F3/19 , H03F3/21 , H03F3/245 , H03F2200/222 , H03F2200/387 , H03F2200/451 , H03F2200/465 , H03F2200/555 , H03F2201/3212 , H04B1/40
摘要： A power amplifier module includes a driver transistor having first, second, and third terminals, a radio-frequency input port coupled to the first terminal of the driver transistor, a cascode transistor having first, second, and third terminals, the second terminal of the cascode transistor being coupled to the third terminal of the driver transistor, a radio-frequency output port coupled to the second terminal of the cascode transistor, and a coupling path connecting the first terminal of the cascode transistor to the third terminal of the cascode transistor, the coupling path including a capacitor.
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公开(公告)号：US20180062580A1
公开(公告)日：2018-03-01
申请号：US15677327
申请日：2017-08-15
CPC分类号： H03F1/22 , H03F1/3241 , H03F1/56 , H03F3/19 , H03F3/191 , H03F3/21 , H03F3/211 , H03F3/245 , H03F3/45089 , H03F3/72 , H03F2200/111 , H03F2200/222 , H03F2200/318 , H03F2200/387 , H03F2200/411 , H03F2200/451 , H03F2203/21145 , H03F2203/7209
摘要： A cascode power cell for a power amplifier circuit includes a radio frequency signal input node, a radio frequency signal output node, and a plurality of sub-cells each including a first transistor having a collector coupled to the radio frequency signal output node, each of the plurality of sub-cells further including a second transistor having a collector coupled to an emitter of the first transistor at a connection node, and a base coupled to the radio frequency signal input node, the connection nodes for each of the plurality of sub-cells being electrically isolated from one another.
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公开(公告)号：US20170063324A1
公开(公告)日：2017-03-02
申请号：US15250751
申请日：2016-08-29
CPC分类号： H03H7/20
摘要： Circuits, devices and methods are disclosed, including a phase shifter comprising a first node and a second node, and a first transmission line element having an inductance and a variable capacitance on each side of the inductance, the variable capacitance configured to provide a plurality of capacitance values to yield corresponding phase shift values based on an increment having a magnitude that is less than 90 degrees. In some implementations, the phase shifter further comprises a second transmission line element in series with the first transmission line element, the second transmission line element having an inductance and a variable capacitance on each side of the inductance configured to extend an overall phase shift range provided by the phase shifter.
摘要翻译： 公开了电路，装置和方法，包括包括第一节点和第二节点的移相器和在电感的每一侧具有电感和可变电容的第一传输线元件，所述可变电容被配置为提供多个 电容值，以基于具有小于90度的幅度的增量产生相应的相移值。 在一些实施方案中，移相器还包括与第一传输线元件串联的第二传输线元件，第二传输线元件具有电感和在电感的每一侧上的可变电容，其被配置为延伸所提供的整体相移范围 由移相器。
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公开(公告)号：US20160013797A1
公开(公告)日：2016-01-14
申请号：US14663336
申请日：2015-03-19
发明人： Rachel Nakabugo KATUMBA , Darren Roger FRENETTE , Ardeshir NAMDAR-MEHDIABADI , John William Mitchell ROGERS
IPC分类号： H03L7/085
CPC分类号： H03L7/085 , H03L7/0891 , H03L7/093 , H03L7/197 , H03L7/1974 , H03L7/1978 , H04L7/04
摘要： Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.
摘要翻译： 公开了用于控制频率合成器的系统和方法。 控制系统可以在诸如频率合成器的Frac-N PLL的锁相环（PLL）中实现，以减少或消除参考杂散。 在一些实施例中，这种控制系统可以包括被配置为接收参考信号和反馈信号的相位检测器。 相位检测器可以被配置为产生表示参考信号和反馈信号之间的相位差的第一信号。 控制系统还可以包括配置成基于第一信号产生补偿信号的电荷泵。 控制系统还可以包括配置成基于补偿信号产生输出信号的振荡器。 补偿信号可被配置为减少或基本上消除与频率合成器相关联的一个或多个参考杂散。
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公开(公告)号：US20190273470A1
公开(公告)日：2019-09-05
申请号：US16416082
申请日：2019-05-17
IPC分类号： H03F1/22 , H03F3/24 , H03F3/72 , H03F3/191 , H03F3/21 , H03F3/45 , H03F3/19 , H03F1/32 , H03F1/56
摘要： A radio-frequency device comprises a first radio-frequency signal node, a second radio-frequency signal node, a first power cell path coupled between the first radio-frequency signal node and a ground reference node, the first power cell path including a first transistor having an input terminal coupled to the second radio-frequency signal node, and a second power cell path coupled in parallel with the first power cell path between the first radio-frequency signal node and the ground reference node, the second power cell path including a second transistor having an input terminal coupled to the second radio-frequency signal node and an output terminal that is electrically isolated from an output terminal of the first transistor.
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公开(公告)号：US20170264251A1
公开(公告)日：2017-09-14
申请号：US15453310
申请日：2017-03-08
CPC分类号： H03F3/195 , H03F1/223 , H03F3/245 , H03F3/68 , H03F2200/108 , H03F2200/294 , H03F2200/391 , H03F2200/414 , H03F2200/417 , H03F2200/421 , H03F2200/45 , H03F2200/451 , H03F2200/492 , H04B1/525
摘要： Circuits, devices and methods are disclosed, including radio-frequency circuitry comprising a polar modulator configured to invert a sampled transmitted signal into an inverted sampled transmitted signal, a signal combiner configured to combine the inverted sampled transmitted signal with a received signal and a control logic circuit coupled to the polar modulator, the control logic circuit configured to adjust one or more tuning parameters of the polar modulator for inverting the sampled transmitted signal.
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公开(公告)号：US20170111065A1
公开(公告)日：2017-04-20
申请号：US15285456
申请日：2016-10-04
CPC分类号： H04B1/0475 , H03F1/223 , H03F1/3205 , H03F3/193 , H03F3/211 , H03F3/24 , H03F3/245 , H03F2200/111 , H03F2200/294 , H03F2200/333 , H03F2200/451 , H03F2200/75 , H04B2001/0408
摘要： A radio-frequency module comprises a low-noise amplifier including a common source transistor having a gate node that receives a radio-frequency input signal and a drain node that transmits a combined radio-frequency output signal, and a correction signal input path configured to receive a correction signal and provide the correction signal to a source node of the common source transistor to generate, at least in part, the combined radio-frequency output signal.
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公开(公告)号：US20200083849A1
公开(公告)日：2020-03-12
申请号：US16356453
申请日：2019-03-18
摘要： Circuits, devices and methods are disclosed, including radio-frequency circuitry comprising a polar modulator configured to invert a sampled transmitted signal into an inverted sampled transmitted signal, a signal combiner configured to combine the inverted sampled transmitted signal with a received signal and a control logic circuit coupled to the polar modulator, the control logic circuit configured to adjust one or more tuning parameters of the polar modulator for inverting the sampled transmitted signal.
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公开(公告)号：US20140177770A1
公开(公告)日：2014-06-26
申请号：US14191404
申请日：2014-02-26
发明人： Rachel Nakabugo KATUMBA , Darren Roger FRENETTE , Ardeshir NAMDAR-MEHDIABADI , John William Mitchell ROGERS
CPC分类号： H03L7/085 , H03L7/0891 , H03L7/093 , H03L7/197 , H03L7/1974 , H03L7/1978 , H04L7/04
摘要： Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.
摘要翻译： 公开了用于控制频率合成器的系统和方法。 控制系统可以在诸如频率合成器的Frac-N PLL的锁相环（PLL）中实现，以减少或消除参考杂散。 在一些实施例中，这种控制系统可以包括被配置为接收参考信号和反馈信号的相位检测器。 相位检测器可以被配置为产生表示参考信号和反馈信号之间的相位差的第一信号。 控制系统还可以包括配置成基于第一信号产生补偿信号的电荷泵。 控制系统还可以包括配置成基于补偿信号产生输出信号的振荡器。 补偿信号可被配置为减少或基本上消除与频率合成器相关联的一个或多个参考杂散。
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