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公开(公告)号:US11804474B2
公开(公告)日:2023-10-31
申请号:US17469281
申请日:2021-09-08
申请人: SK hynix Inc.
发明人: Ki Jun Sung , Chae Sung Lee
IPC分类号: H01L25/065 , H01L23/31 , H01L23/00 , H01L25/00
CPC分类号: H01L25/0657 , H01L23/3107 , H01L24/19 , H01L24/20 , H01L25/50 , H01L2225/06548 , H01L2225/06562
摘要: A stack package, and a method of manufacturing the same, includes a first encapsulant layer formed on a carrier. Also semiconductor dies are sequentially offset stacked on the first encapsulant layer. Vertical connectors connected to the semiconductor dies are formed. A second encapsulant layer coupled to the first encapsulant layer is formed to encapsulate the vertical connectors and the semiconductor dies. Redistribution layers connected to the vertical connectors are formed on the second encapsulant layer.
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公开(公告)号:US09153557B2
公开(公告)日:2015-10-06
申请号:US14452323
申请日:2014-08-05
申请人: SK HYNIX INC.
发明人: Ki Jun Sung , Seung Jee Kim , Jong Hyun Nam , Sang Yong Lee , Young Geun Yoo
IPC分类号: H01L23/00 , H01L25/065
CPC分类号: H01L25/0652 , H01L23/13 , H01L23/24 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/19 , H01L24/73 , H01L24/92 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2224/04105 , H01L2224/13009 , H01L2224/16145 , H01L2224/16146 , H01L2224/16235 , H01L2224/17181 , H01L2224/32225 , H01L2224/73253 , H01L2224/73259 , H01L2224/92224 , H01L2224/92242 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06548 , H01L2225/06562 , H01L2225/06589 , H01L2924/0002 , H01L2924/15156 , H01L2924/3511
摘要: A chip stack embedded package includes a first dielectric layer having a multistep cavity therein, a first plurality of semiconductor chips disposed in a first level of the multistep cavity, a second plurality of semiconductor chips disposed in a second level of the multistep cavity, and a second dielectric layer filling the multistep cavity to cover the first and second pluralities of semiconductor chips.
摘要翻译: 芯片堆叠嵌入式封装包括其中具有多级空腔的第一介电层,设置在多级腔的第一级中的第一多个半导体芯片,设置在多级腔的第二级中的第二多个半导体芯片,以及 填充多阶空腔以覆盖第一和第二多个半导体芯片的第二介电层。
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公开(公告)号:US10903131B2
公开(公告)日:2021-01-26
申请号:US16197130
申请日:2018-11-20
申请人: SK hynix Inc.
发明人: Ki Jun Sung , Sungkyu Kim
IPC分类号: H01L23/31 , H01L23/538 , H01L21/56 , H01L23/00
摘要: A semiconductor package includes a semiconductor die and a bridge die. The bridge die includes through vias, and the through vias are connected to post bumps. The through vias are electrically connected to the semiconductor die by redistribution lines.
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公开(公告)号:US09922965B2
公开(公告)日:2018-03-20
申请号:US15487078
申请日:2017-04-13
申请人: SK hynix Inc.
发明人: Jong Hoon Kim , Ki Jun Sung , Young Geun Yoo , Hyeong Seok Choi
CPC分类号: H01L25/105 , H01L21/31058 , H01L21/4853 , H01L21/565 , H01L23/3128 , H01L23/49811 , H01L23/5385 , H01L23/5389 , H01L25/0657 , H01L25/50 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2225/1088 , H01L2924/15311 , H01L2924/15313 , H01L2924/15331 , H01L2924/1815 , H01L2924/00014 , H01L2224/32225 , H01L2924/00012
摘要: A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. A portion of the first mold layer is removed to expose top portions of the first bumps and second bumps are disposed to be connected to each of the first bumps. A second mold layer is formed, and the second mold layer is recessed to form through mold connectors that substantially penetrate the second mold layer with the second bumps disposed on the first bumps.
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公开(公告)号:US09847285B1
公开(公告)日:2017-12-19
申请号:US15435951
申请日:2017-02-17
申请人: SK hynix Inc.
发明人: Ki Jun Sung , Jong Hoon Kim , Han Jun Bae
IPC分类号: H01L23/498 , H01L23/31 , H01L23/367 , H01L23/00
CPC分类号: H01L23/49816 , H01L21/4857 , H01L21/486 , H01L21/561 , H01L21/568 , H01L23/147 , H01L23/15 , H01L23/3128 , H01L23/367 , H01L23/3677 , H01L23/49811 , H01L23/5383 , H01L23/5384 , H01L23/5389 , H01L24/17 , H01L2224/16225 , H01L2224/73253 , H01L2924/01029 , H01L2924/15311 , H01L2924/15321 , H01L2924/18161
摘要: There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball connectors (TMBCs) on a first surface of an interconnection structure layer, forming a molding layer on the first surface of the interconnection structure layer to expose a portion of each of the TMBCs, attaching outer connectors to the exposed portions of the TMBCs, mounting a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer, and attaching a heat spreader to the second surface of the interconnection structure layer to overlap with a portion of the first semiconductor device.
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公开(公告)号:US09806015B1
公开(公告)日:2017-10-31
申请号:US15419267
申请日:2017-01-30
申请人: SK hynix Inc.
发明人: Ki Jun Sung , Jong Hoon Kim , Han Jun Bae
IPC分类号: H01L21/00 , H01L23/02 , H01L23/498 , H01L23/31 , H01L25/065 , H01L25/18 , H01L21/48 , H01L21/56 , H01L25/00 , H01L23/00 , H01L25/07 , H01L25/11
CPC分类号: H01L23/49838 , H01L21/4853 , H01L21/4857 , H01L21/486 , H01L21/565 , H01L23/3114 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L23/562 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/071 , H01L25/112 , H01L25/18 , H01L25/50 , H01L2224/13025 , H01L2224/13147 , H01L2224/1403 , H01L2224/14181 , H01L2224/16146 , H01L2224/16227 , H01L2224/73253 , H01L2225/06572 , H01L2924/15192 , H01L2924/15311 , H01L2924/1532 , H01L2924/16251 , H01L2924/18161
摘要: A semiconductor package includes first bump pads on a first surface of an interconnection structure layer, elevated pads thicker than the first bump pads on the first surface of the interconnection structure layer, a first semiconductor device connected on the first bump pads, through mold ball connectors connected on the elevated pads, respectively, a molding layer disposed covering the first surface of the interconnection structure layer to expose a portion of each of the through mold ball connectors, outer connectors respectively attached to the through mold ball connectors, and a second semiconductor device on a second surface of the interconnection structure layer opposite to the molding layer.
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公开(公告)号:US11322446B2
公开(公告)日:2022-05-03
申请号:US16665970
申请日:2019-10-28
申请人: SK hynix Inc.
发明人: Jong Hoon Kim , Ki Jun Sung , Ki Bum Kim
IPC分类号: H01L23/31 , H01L23/538 , H01L23/48 , H01L25/18 , H01L23/00
摘要: A system-in-package includes a redistributed line (RDL) structure, a first semiconductor chip, a second semiconductor chip, and a bridge die. The RDL structure includes a first RDL pattern to which a first chip pad of the first semiconductor chip is electrically connected. The second semiconductor chip is stacked on the first semiconductor chip such that the second semiconductor chip protrudes past a side surface of the first semiconductor chip, wherein a second chip pad disposed on the protrusion is electrically connected to the first RDL pattern through the bridge die.
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公开(公告)号:US10985106B2
公开(公告)日:2021-04-20
申请号:US16216778
申请日:2018-12-11
申请人: SK hynix Inc.
发明人: Ki Jun Sung , Ha Gyeong Song
IPC分类号: H01L23/538 , H01L25/065 , H01L23/00 , H01L23/29 , H01L23/31
摘要: A stack package includes a plurality of sub-packages vertically stacked. Each of the sub-packages includes a bridge die having a plurality of vertical interconnectors and a semiconductor die. A first group of vertical interconnectors disposed in a first bridge die included in a first sub-package of the sub-packages and other vertical interconnectors connected to the first group of vertical interconnectors constitute a first electric path, and a second group of vertical interconnectors disposed in a second bridge die included in a second sub-package of the sub-packages and other vertical interconnectors connected to the second group of vertical interconnectors constitute a second electric path. The first and second electric paths are electrically isolated from each other and disposed to provide two separate electric paths.
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公开(公告)号:US10903196B2
公开(公告)日:2021-01-26
申请号:US16690816
申请日:2019-11-21
申请人: SK hynix Inc.
发明人: Ki Jun Sung , Sang Hyuk Lim
IPC分类号: H01L25/10 , H01L23/498 , H01L23/31 , H01L23/538
摘要: A semiconductor package includes first and second semiconductor dies, first and second redistributed line structures, a first bridge die, and a vertical connector. The first semiconductor die and the first bridge die are disposed on the first redistributed line structure. The first bridge die is disposed to provide a level difference between the first semiconductor die and the first bridge die, the first bridge die having a height that is less than a height of the first semiconductor die. The second redistributed line structure has a protrusion, laterally protruding from a side surface of the first semiconductor die when viewed from a plan view, and a bottom surface of the second redistributed line structure is in contact with a top surface of the first semiconductor die. The second semiconductor die is disposed on the second redistributed line structure. The vertical connector is disposed between the bridge die and the protrusion of the second redistributed line structure to support the protrusion.
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公开(公告)号:US09659910B1
公开(公告)日:2017-05-23
申请号:US15167383
申请日:2016-05-27
申请人: SK hynix Inc.
发明人: Jong Hoon Kim , Ki Jun Sung , Young Geun Yoo , Hyeong Seok Choi
IPC分类号: H01L21/00 , H01L25/065 , H01L25/00 , H01L21/48 , H01L21/56 , H01L23/00 , H01L21/3105 , H01L23/498 , H01L23/31
CPC分类号: H01L25/105 , H01L21/31058 , H01L21/4853 , H01L21/565 , H01L23/3128 , H01L23/49811 , H01L23/5385 , H01L23/5389 , H01L25/0657 , H01L25/50 , H01L2224/16227 , H01L2224/16235 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1035 , H01L2225/1058 , H01L2225/1088 , H01L2924/15311 , H01L2924/15313 , H01L2924/15331 , H01L2924/1815 , H01L2924/00014 , H01L2224/32225 , H01L2924/00012
摘要: A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. A portion of the first mold layer is removed to expose top portions of the first bumps and second bumps are disposed to be connected to each of the first bumps. A second mold layer is formed, and the second mold layer is recessed to form through mold connectors that substantially penetrate the second mold layer with the second bumps disposed on the first bumps.
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