公开(公告)号：US11444063B2

公开(公告)日：2022-09-13

申请号：US17308718

申请日：2021-05-05

申请人： SK hynix Inc.

发明人： Ki Jun Sung ,  Chae Sung Lee

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538

摘要： A semiconductor package may include: at least one semiconductor chip disposed such that an active surface on which a plurality of chip pads are disposed faces a redistribution conductive layer; a plurality of vertical interconnectors, each with one end connected to a respective chip pad, extending in a vertical direction toward the redistribution conductive layer; a molding layer covering the semiconductor chip and the vertical interconnectors while exposing an other end of each of the vertical interconnectors that is not connected to the chip pad; a plurality of landing pads disposed over the molding layer, and each connected to the other end of each of the vertical interconnectors; a redistribution insulating layer covering the molding layer with an opening that collectively exposes the landing pads; and the redistribution conductive layer that extends over the molding layer and the redistribution insulating layer while being connected to each of the landing pads.

公开(公告)号：US11804474B2

公开(公告)日：2023-10-31

申请号：US17469281

申请日：2021-09-08

申请人： SK hynix Inc.

发明人： Ki Jun Sung ,  Chae Sung Lee

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00

CPC分类号： H01L25/0657 ,  H01L23/3107 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H01L2225/06548 ,  H01L2225/06562

摘要： A stack package, and a method of manufacturing the same, includes a first encapsulant layer formed on a carrier. Also semiconductor dies are sequentially offset stacked on the first encapsulant layer. Vertical connectors connected to the semiconductor dies are formed. A second encapsulant layer coupled to the first encapsulant layer is formed to encapsulate the vertical connectors and the semiconductor dies. Redistribution layers connected to the vertical connectors are formed on the second encapsulant layer.

公开(公告)号：US11784162B2

公开(公告)日：2023-10-10

申请号：US17154705

申请日：2021-01-21

申请人： SK hynix Inc.

发明人： Tae Hoon Kim ,  Chae Sung Lee

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L23/3107 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/48227 ,  H01L2225/06562

摘要： A semiconductor package includes at least one semiconductor chip disposed in such a way that an active surface with chip pads faces a redistribution layer, vertical interconnectors extending in a vertical direction from the chip pads toward the redistribution layer, wherein each of the vertical connectors has a first end portion that is connected to a corresponding chip pad and a second end portion that is disposed on an opposite end of each vertical interconnector in relation to the first end portion, and a molding layer covering the semiconductor chip and the vertical interconnectors while exposing a surface of each of the second end portions of the vertical interconnectors, wherein the redistribution layer is formed over the molding layer, the redistribution layer having a redistribution land that is in contact with the surface of the second end portion, and wherein a width of the surface of the second end portion is greater than a width of an extension portion between the first end portion and the second end portion of each vertical interconnector.

公开(公告)号：US11502028B2

公开(公告)日：2022-11-15

申请号：US17175914

申请日：2021-02-15

申请人： SK hynix Inc.

发明人： Chae Sung Lee ,  Jong Hoon Kim

IPC分类号： H01L21/00 ,  H01L23/02 ,  H01L25/065 ,  H01L23/498 ,  H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/78 ,  H01L21/56 ,  H01L23/00

摘要： A semiconductor package is described. The semiconductor packager includes a chip stack mounted over a package substrate, a first wire disposed over the package substrate, and a molding layer surrounding the chip stack and the first wire. The first wire has an acute angle.