公开(公告)号：US12125914B2

公开(公告)日：2024-10-22

申请号：US18213781

申请日：2023-06-23

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Clifford Drowley ,  Ray Milano ,  Subhash Srinivas Pidaparthi ,  Andrew P. Edwards ,  Hao Cui ,  Shahin Sharifzadeh

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/778

CPC分类号： H01L29/7856 ,  H01L29/6653 ,  H01L29/66803 ,  H01L29/7783 ,  H01L29/7788

摘要： A method of fabricating a vertical fin-based field effect transistor (FET) includes providing a semiconductor substrate having a first surface and a second surface, the semiconductor substrate having a first conductivity type, epitaxially growing a first semiconductor layer on the first surface of the semiconductor substrate, the first semiconductor layer having the first conductivity type and including a drift layer and a graded doping layer on the drift layer, and epitaxially growing a second semiconductor layer having the first conductivity type on the graded doping layer. The method also includes forming a metal compound layer on the second semiconductor layer, forming a patterned hard mask layer on the metal compound layer, and etching the metal compound layer and the second semiconductor layer using the patterned hard mask layer as a mask exposing a surface of the graded doping layer to form a plurality of fins surrounded by a trench.

公开(公告)号：US20240274725A1

公开(公告)日：2024-08-15

申请号：US18600234

申请日：2024-03-08

申请人： Semiconductor Components Industries, LLC

发明人： Clifford Drowley ,  Andrew P. Edwards ,  Subhash Srinivas Pidaparthi ,  Ray Milano

IPC分类号： H01L29/808 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/8083 ,  H01L27/0676 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/2003 ,  H01L29/66909 ,  H01L29/785

摘要： Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.

公开(公告)号：US11996407B2

公开(公告)日：2024-05-28

申请号：US17373627

申请日：2021-07-12

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Clifford Drowley ,  Hao Cui ,  Andrew P. Edwards ,  Subhash Srinivas Pidaparthi

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

摘要： A method for manufacturing a vertical FET device includes providing a semiconductor substrate structure including a semiconductor substrate and a first semiconductor layer coupled to the semiconductor substrate. The first semiconductor layer is characterized by a first conductivity type. The method also includes forming a plurality of semiconductor fins coupled to the first semiconductor layer. Each of the plurality of semiconductor fins is separated by one of a plurality of recess regions. The method further includes epitaxially regrowing a semiconductor gate layer including a surface region in the plurality of recess regions. The method also includes forming an isolation region within the surface region of the semiconductor gate layer. The isolation region surrounds each of the plurality of semiconductor fins. The method includes forming a source contact structure coupled to each of the plurality of semiconductor fins and forming a gate contact structure coupled to the semiconductor gate layer.

公开(公告)号：US20240274545A1

公开(公告)日：2024-08-15

申请号：US18602684

申请日：2024-03-12

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Clifford Drowley ,  Ray Milano ,  Robert Routh ,  Subhash Srinivas Pidaparthi ,  Andrew P. Edwards

IPC分类号： H01L23/544 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L23/544 ,  H01L21/02389 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785 ,  H01L2223/54426

摘要： A method of forming alignment marks includes providing a III-V compound substrate having a device region and an alignment mark region, forming a hardmask layer having a first set of openings on the alignment mark region exposing a first surface portion of the III-V compound substrate and a second set of openings on the device region exposing a second surface portion of the III-V compound substrate, etching the exposed surface of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches, and epitaxially regrowing a semiconductor layer in the trenches to form the alignment marks extending to a predetermined height over the processing surface of the III-V compound substrate.

公开(公告)号：US20240258408A1

公开(公告)日：2024-08-01

申请号：US18587327

申请日：2024-02-26

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Clifford Drowley ,  Ray Milano ,  Subhash Srinivas Pidaparthi ,  Andrew P. Edwards

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/20 ,  H01L29/808

CPC分类号： H01L29/66924 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/30612 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/66909 ,  H01L29/8083

摘要： A method of fabricating a semiconductor device includes providing a substrate structure comprising a semiconductor substrate of a first conductivity type, a drift layer on the semiconductor substrate, and a fin array on the drift layer and surrounded by a recess region. The fin array comprises a first row of fins and a second row of fins parallel to each other and separated from each other by a space. The first row of fins comprises a plurality of first elongated fins extending parallel to each other in a first direction. The second row of fins comprises a plurality of second elongated fins extending parallel to each other in a second direction parallel to the first direction. The method also includes epitaxially regrowing a gate layer surrounding the first and second row of fins on the drift layer and filling the recess region.

公开(公告)号：US12080757B2

公开(公告)日：2024-09-03

申请号：US18371956

申请日：2023-09-22

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Hao Cui ,  Clifford Drowley

IPC分类号： H01L21/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/808 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306

CPC分类号： H01L29/0634 ,  H01L29/66522 ,  H01L29/66734 ,  H01L29/66909 ,  H01L29/66924 ,  H01L29/7813 ,  H01L29/8083 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/02496 ,  H01L21/02502 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02642 ,  H01L21/28264 ,  H01L21/30617

摘要： A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type and forming a first III-nitride layer coupled to the III-nitride substrate. The first III-nitride layer is characterized by a first dopant concentration and the first conductivity type. The method also includes forming a plurality of trenches within the first III-nitride layer and epitaxially regrowing a second III-nitride structure in the trenches. The second III-nitride structure is characterized by a second conductivity type. The method further includes forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions, and epitaxially regrowing a III-nitride gate layer in the recess regions. The III-nitride gate layer is coupled to the second III-nitride structure and the III-nitride gate layer is characterized by the second conductivity type.

公开(公告)号：US12113101B2

公开(公告)日：2024-10-08

申请号：US17369600

申请日：2021-07-07

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Subhash Srinivas Pidaparthi ,  Andrew P. Edwards ,  Clifford Drowley ,  Kedar Patel

IPC分类号： H01L29/06 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/40

CPC分类号： H01L29/0615 ,  H01L21/26546 ,  H01L21/266 ,  H01L21/3245 ,  H01L29/401 ,  H01L29/402

摘要： A method for manufacturing a semiconductor device includes: providing a semiconductor substrate; epitaxially growing a first semiconductor layer coupled to the semiconductor substrate; epitaxially growing a second semiconductor layer coupled to the first semiconductor layer, wherein the second semiconductor layer comprises a contact region and a terminal region surrounding the contact region; forming a mask layer on the second semiconductor layer, wherein the mask layer is patterned with a tapered region aligned with the terminal region of the second semiconductor layer; implanting ions into the terminal region of the second semiconductor layer using the mask layer to form a tapered junction termination element in the terminal region of the second semiconductor layer; and forming a contact structure in the contact region of the second semiconductor layer.