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    SMT PACKAGES AND SMT SUBSTRATES INCLUDED IN SMT PACKAGES
    1.
    发明申请
    SMT PACKAGES AND SMT SUBSTRATES INCLUDED IN SMT PACKAGES 有权

    公开(公告)号：US20240421057A1

    公开(公告)日：2024-12-19

    申请号：US18591183

    申请日：2024-02-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jinhyung Jung ,  Hyonchol Kim ,  Won Choi

    IPC: H01L23/498

    Abstract: A surface mount technology (SMT) package includes an SMT substrate including an interconnection layer, an insulating layer having an arrangement region for the interconnection layer, and a mask layer on an upper surface of the insulating layer, a component including an insulating body, and an external electrode having at least a portion on a surface of the insulating body opposing the SMT substrate, and a solder that electrically connects the interconnection layer and the external electrode to each other. The mask layer has an opening, and the SMT substrate further includes an insulating support that supports the external electrode in the opening such that the external electrode is spaced apart from the interconnection layer and the insulating layer.

    Semiconductor package
    3.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11189567B2

    公开(公告)日：2021-11-30

    申请号：US16580240

    申请日：2019-09-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Pyung Hwa Han ,  Jung Soo Kim ,  Won Choi ,  Sung Hawn Bae

    IPC: H01L23/528 ,  H01L23/544 ,  H01L23/522 ,  H01L23/31 ,  H01L23/00

    Abstract: A semiconductor package includes: a connection structure having first and second surfaces opposing each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure, encapsulating the semiconductor chip, and including an opaque or translucent resin; a mark indicating identification information and carved in the encapsulant; and a passivation layer disposed on the encapsulant and including a transparent resin.

    Fan-out semiconductor package
    5.
    发明授权
    Fan-out semiconductor package 有权

    公开(公告)号：US10665549B2

    公开(公告)日：2020-05-26

    申请号：US16268874

    申请日：2019-02-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung Hawn Bae ,  Jung Soo Kim ,  Won Choi ,  Sung Hoan Kim

    IPC: H01L23/52 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L25/18

    Abstract: A fan-out semiconductor package includes: a frame, including a wiring layer, and having a through-hole; a semiconductor chip disposed in the through-hole, and including a connection pad; an encapsulant covering at least a portion of each of the frame and an inactive surface of the semiconductor chip, and having a first opening exposing at least a portion of the wiring layer; an insulating layer disposed on the encapsulant, and having a second opening formed in the first opening to expose at least a portion of the wiring layer; a conductive pattern layer disposed on the insulating layer; a conductive via disposed in the second opening; and a connection structure disposed on the frame and an active surface of the semiconductor chip, and including one or more redistribution layers. The conductive pattern layer and the redistribution layer are electrically connected to the connection pad.

    FAN-OUT SEMICONDUCTOR PACKAGE
    9.
    发明申请
    FAN-OUT SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20200051918A1

    公开(公告)日：2020-02-13

    申请号：US16268874

    申请日：2019-02-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sung Hawn Bae ,  Jung Soo Kim ,  Won Choi ,  Sung Hoan Kim

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L25/18

    Abstract: A fan-out semiconductor package includes: a frame, including a wiring layer, and having a through-hole; a semiconductor chip disposed in the through-hole, and including a connection pad; an encapsulant covering at least a portion of each of the frame and an inactive surface of the semiconductor chip, and having a first opening exposing at least a portion of the wiring layer; an insulating layer disposed on the encapsulant, and having a second opening formed in the first opening to expose at least a portion of the wiring layer; a conductive pattern layer disposed on the insulating layer; a conductive via disposed in the second opening; and a connection structure disposed on the frame and an active surface of the semiconductor chip, and including one or more redistribution layers. The conductive pattern layer and the redistribution layer are electrically connected to the connection pad.

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