公开(公告)号：US20220028834A1

公开(公告)日：2022-01-27

申请号：US17245913

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： HYUEKJAE LEE ,  UN-BYOUNG KANG ,  SANG CHEON PARK ,  JINKYEONG SEOL ,  SANGHOON LEE

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package is provided. The semiconductor package may include a first semiconductor die, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a width smaller than a width of the first semiconductor die, a third semiconductor die stacked on the second semiconductor die, the third semiconductor die having a width smaller than the width of the first semiconductor die, and a mold layer covering side surfaces of the second and third semiconductor dies and a top surface of the first semiconductor die. The second semiconductor die may include a second through via, and the third semiconductor die may include a third conductive pad in contact with the second through via.

公开(公告)号：US20150137251A1

公开(公告)日：2015-05-21

申请号：US14454476

申请日：2014-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGHEE LEE ,  EUI-CHUL JEONG ,  NARA KIM ,  SEUNG HWAN KIM ,  DONGWOO WOO ,  SANGHOON LEE ,  SUNGJOO LEE

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/423 ,  H01L27/108 ,  H01L21/762

CPC classification number: H01L29/7846 ,  H01L21/76224 ,  H01L27/10876 ,  H01L27/10888 ,  H01L29/4236 ,  H01L29/66621

Abstract: A semiconductor device includes a substrate and a device isolation pattern extending from a surface of the substrate into the substrate. The device isolation pattern has an electrically negative property and a physically tensile property. The device isolation pattern delimits an active region of the substrate. A transistor is provided at the active region and has a channel region formed by part of the active region.

Abstract translation: 半导体器件包括从衬底的表面延伸到衬底中的衬底和器件隔离图案。 器件隔离图案具有电负性质和物理拉伸特性。 器件隔离图案限定衬底的有源区。 晶体管设置在有源区，并具有由有源区的一部分形成的沟道区。

公开(公告)号：US20210335779A1

公开(公告)日：2021-10-28

申请号：US17371494

申请日：2021-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOCHEOL SHIN ,  MYUNGGIL KANG ,  MINYI KIM ,  SANGHOON LEE

IPC: H01L27/06 ,  H01L21/8234

Abstract: A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.

公开(公告)号：US20190355741A1

公开(公告)日：2019-11-21

申请号：US16217696

申请日：2018-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANGHOON LEE ,  SUNGGIL KIM ,  SEULYE KIM ,  HWAEON SHIN ,  JOONSUK LEE ,  HYEEUN HONG

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/10 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The method includes sequentially forming a sacrificial pattern and a source conductive layer on a substrate, forming a mold structure including a plurality of insulating layers and a plurality of sacrificial layers on the source conductive layer; forming a plurality of vertical structures that penetrate the mold structure, forming a trench that penetrates the mold structure, forming a sacrificial spacer on a sidewall of the trench, removing the sacrificial pattern to form a horizontal recess region; removing the sacrificial spacer, and forming a source conductive pattern that fills the horizontal recess region.

公开(公告)号：US20190081054A1

公开(公告)日：2019-03-14

申请号：US15981928

申请日：2018-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGGIL KIM ,  SANGSOO LEE ,  SEULYE KIM ,  HONGSUK KIM ,  JINTAE NOH ,  JI-HOON CHOI ,  JAEYOUNG AHN ,  SANGHOON LEE

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor memory device has a plurality of gates vertically stacked on a top surface of a substrate, a vertical channel filling a vertical hole that extends vertically through the plurality of gates, and a memory layer in the vertical hole and surrounding the vertical channel. The vertical channel includes a bracket-shaped lower portion filling part of a recess in the top of the substrate and an upper portion extending vertically along the vertical hole and connected to the lower channel. At least one end of an interface between the lower and upper portions of the vertical channel is disposed at a level not than that of the top surface of the substrate.

公开(公告)号：US20240105679A1

公开(公告)日：2024-03-28

申请号：US18135035

申请日：2023-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG KUN JEE ,  SANGHOON LEE ,  UN-BYOUNG KANG ,  SANG CHEON PARK ,  JUMYONG PARK ,  HYUNCHUL JUNG

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/03 ,  H01L2224/08146 ,  H01L2225/06541

Abstract: Disclosed are semiconductor packages and their fabrication methods. The semiconductor package comprises providing a semiconductor substrate, forming a semiconductor element on an active surface of the semiconductor substrate, forming in the semiconductor substrate through vias that extend from the active surface into the semiconductor substrate, forming a first pad layer on the active surface of the semiconductor substrate, performing a first planarization process on the first pad layer, performing on an inactive surface of the semiconductor substrate a thinning process to expose the through vias, forming a second pad layer on the inactive surface of the semiconductor substrate, performing a second planarization process on the second pad layer, and after the second planarization process, performing a third planarization process on the first pad layer.

公开(公告)号：US20230144507A1

公开(公告)日：2023-05-11

申请号：US18148810

申请日：2022-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOCHEOL SHIN ,  MYUNGGIL KANG ,  MINYI KIM ,  SANGHOON LEE

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L27/0629 ,  H01L21/823481 ,  H01L21/823431

Abstract: A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.

公开(公告)号：US20230333160A1

公开(公告)日：2023-10-19

申请号：US18075542

申请日：2022-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYUNG-SUNG KIM ,  YUN-HYOK CHOI ,  GYUYEOL KIM ,  SUNGJUNG KIM ,  CHEOL-HEUI PARK ,  SANGHOON LEE ,  JAE-WOONG CHOI

IPC: G01R31/3177 ,  G04F10/00

CPC classification number: G01R31/3177 ,  G04F10/005

Abstract: Disclosed is a fan-out buffer which includes a first channel that includes a first delay circuit adjusting a first delay time of a calibration test signal depending on a first delay control signal, a second channel that includes a second delay circuit adjusting a second delay time of the calibration test signal depending on a second delay control signal, a first edge-to-pulse converter that detects a first edge included in a first time domain reflectometry (TDR) waveform of an output terminal of the first channel and generates a first start pulse signal including a first pulse, a second edge-to-pulse converter that generates a second start pulse signal including a second pulse, a stop pulse signal generator that generates a stop pulse signal including a first stop pulse, and a first delay control signal generator that calculates a phase difference generates the first delay control signal.

公开(公告)号：US20210028164A1

公开(公告)日：2021-01-28

申请号：US16784788

申请日：2020-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOCHEOL SHIN ,  MYUNGGIL KANG ,  MINYI KIM ,  SANGHOON LEE

IPC: H01L27/06 ,  H01L21/8234

Abstract: A resistor including a device isolation layer is described that includes a first active region and a second active region, a buried insulating layer, and an N well region. The N well region surrounds the first active region, the second active region, the device isolation layer and the buried insulating layer. A first doped region and a second doped region are disposed on the first active region and the second active region. The first doped region and the second doped region are in contact with the N well region and include n type impurities.