公开(公告)号：US20230275037A1

公开(公告)日：2023-08-31

申请号：US18144902

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L23/544 ,  H01L21/78 ,  H01L2223/5446

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

公开(公告)号：US09859163B2

公开(公告)日：2018-01-02

申请号：US15235175

申请日：2016-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyounghoon Han ,  Junho Yoon ,  Kisoo Chang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L21/311 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/31144 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for manufacturing a semiconductor device includes forming gate structures spaced apart from each other on a substrate, gate spacers covering sidewalls of the gate structures, and an interlayer insulating layer covering the gate spacers, forming a contact hole that penetrates the interlayer insulating layer to expose a sidewall of at least one of the gate spacers, forming a sacrificial gap-fill pattern filling a lower portion of the contact hole, forming a contact spacer on a sidewall of the contact hole having the sacrificial gap-fill pattern, and forming a contact filling the contact hole after removing the sacrificial gap-fill pattern.

公开(公告)号：US20140065784A1

公开(公告)日：2014-03-06

申请号：US13952207

申请日：2013-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Dongchan Kim ,  Gyungjin Min ,  Jaehong Park ,  Yongmoon Jang ,  Je-Woo Han

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L28/90

Abstract: A method of fabricating a semiconductor device with capacitors may include forming a mold structure on a lower structure, patterning the mold structure to form a plurality of holes exposing the lower structure, forming a protection layer on sidewalls of the mold structure exposed by the holes, forming lower electrodes in the holes provided with the protection layer, removing the mold structure to expose the protection layer, removing the protection layer to expose sidewalls of the lower electrodes, and sequentially forming a dielectric film and an upper electrode on the lower electrodes.

Abstract translation: 制造具有电容器的半导体器件的方法可以包括在下部结构上形成模具结构，图案化模具结构以形成暴露下部结构的多个孔，在由孔露出的模具结构的侧壁上形成保护层， 在设置有保护层的孔中形成下电极，去除模具结构以露出​​保护层，去除保护层以暴露下电极的侧壁，并且在下电极上依次形成电介质膜和上电极。

公开(公告)号：US20240355678A1

公开(公告)日：2024-10-24

申请号：US18636463

申请日：2024-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Junyun Kweon ,  Haemin Park ,  Kwangyong Lee ,  Jesung Kim ,  Dayoung Cho

IPC: H01L21/78 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor chip includes an active layer on a top surface of an underlying base substrate. The active layer has: bonding surface therein that delineates an interface between a bottom active layer and a top active layer extending on the bottom active layer, and a chamfered edge that extends entirely through the top active layer to fully expose a sidewall thereof but only partially through the bottom active layer, such that the chamfered edge has a vertical height greater than a thickness of the top active layer but less than a combined thickness of the top and bottom active layers. A protective layer is also provided, which covers at least a portion of a top surface of the active layer. A vertical level of a bottom of the chamfered edge may be higher than a vertical level of the top surface of the base substrate.

公开(公告)号：US12062626B2

公开(公告)日：2024-08-13

申请号：US18144902

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/544 ,  H01L2223/5446

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

公开(公告)号：US10607820B2

公开(公告)日：2020-03-31

申请号：US15400126

申请日：2017-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Jaehyun Lee

IPC: H01L21/00 ,  H01J37/32 ,  G01N29/12 ,  G01N29/24 ,  H01L21/3065 ,  H01L21/66

Abstract: A monitoring unit for monitoring a plasma process chamber includes a piezoelectric member comprising a surface that is exposed within the plasma process chamber, a first electrode coupled to the piezoelectric member, a power supply unit coupled to the first electrode and configured to apply a voltage to the piezoelectric member through the first electrode, and a control unit coupled to the piezoelectric member and configured to detect a vibration frequency of the piezoelectric member. The vibration frequency is generated in response to the voltage applied to the piezoelectric member.

公开(公告)号：US20240178000A1

公开(公告)日：2024-05-30

申请号：US18519501

申请日：2023-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jesung Kim ,  Haemin Park ,  Heejae Nam ,  Junggeun Shin ,  Junho Yoon ,  Jungho Choi

IPC: H01L21/304 ,  B23K26/53 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L21/3043 ,  B23K26/53 ,  H01L21/6836 ,  H01L21/78 ,  B23K2101/40 ,  H01L2221/68327

Abstract: A wafer dicing method includes preparing a wafer having a plurality of device formation areas and a scribe lane area defining the plurality of device formation areas, forming a plurality of semiconductor devices in the plurality of device formation areas of the wafer, forming, in the scribe lane area, a plurality of first grooves partially passing through at least a portion of the wafer in a vertical direction, forming a plurality of second grooves by planarizing lower surfaces of the plurality of first grooves, forming one or more internal cracks in the wafer by radiating a laser beam along lower surfaces of the plurality of second grooves, and separating the plurality of semiconductor devices from each other along the one or more internal cracks.

公开(公告)号：US11676914B2

公开(公告)日：2023-06-13

申请号：US17216279

申请日：2021-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/544 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/544 ,  H01L2223/5446

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

公开(公告)号：US09812335B2

公开(公告)日：2017-11-07

申请号：US15066492

申请日：2016-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Woo Han ,  Junho Yoon ,  Kyohyeok Kim ,  Dongchan Kim ,  Sungyeon Kim ,  Jaehong Park ,  Jinyoung Park ,  KyungYub Jeon

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31144 ,  H01L21/31116 ,  H01L21/76816

Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming an target layer on a substrate, forming a mask pattern on a target layer, performing a first process to etch the target layer and form a first sub-trench, and performing a second process to further etch the target layer and form a second sub-trench. First and second sidewall patterns may be formed on a sidewall of the mask pattern to be used as an etch mask in the first and second processes, respectively. Outer sidewalls of the first and second sidewall patterns may be formed to have different angles with respect to a top surface of the substrate.

公开(公告)号：US09647056B2

公开(公告)日：2017-05-09

申请号：US14961994

申请日：2015-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Gyungjin Min ,  Jaehong Park ,  Yongmoon Jang ,  Je-Woo Han

IPC: H01L29/92 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/56 ,  H01L28/91 ,  H01L28/92

Abstract: Semiconductor devices are provided. Each of the semiconductor devices may include a plurality of electrodes. Moreover, each of the semiconductor devices may include a supporting pattern connected to sidewalls of the plurality of electrodes. Related methods of forming semiconductor devices are also provided. For example, the methods may include forming the supporting pattern before forming the plurality of electrodes.