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    Methods of forming semiconductor devices using hard masks
    1.
    发明授权
    Methods of forming semiconductor devices using hard masks 有权
    使用硬掩模形成半导体器件的方法

    公开(公告)号：US09305802B2

    公开(公告)日：2016-04-05

    申请号：US14510331

    申请日：2014-10-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongchan Kim ,  Gyungjin Min ,  Minjoon Park ,  Seunghoon Park ,  KeunHee Bai ,  Kisoo Chang

    IPC: H01L21/31 ,  H01L21/311 ,  H01L21/3213

    CPC classification number: H01L21/31111 ,  H01L21/31122 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/66795

    Abstract: Methods of forming a semiconductor device are provided. The methods may include forming an insulating layer including silicon on a substrate and sequentially forming a first hard mask layer and a second hard mask layer on the substrate. The first hard mask layer may include carbon, and the second hard mask layer may include carbon and impurities. The first and second hard mask layers may expose at least a portion of the insulating layer. The methods may also include performing an etching process to selectively remove the second hard mask layer with respect to the insulating layer. A ratio of etch rates between the second hard mask layer and the insulating layer during the etching process may be in a range of about 100:1 to about 10,000:1.

    Abstract translation: 提供了形成半导体器件的方法。 所述方法可以包括在衬底上形成包括硅的绝缘层，并且在衬底上依次形成第一硬掩模层和第二硬掩模层。 第一硬掩模层可以包括碳，第二硬掩模层可以包括碳和杂质。 第一和第二硬掩模层可以暴露绝缘层的至少一部分。 所述方法还可以包括执行蚀刻工艺以相对于绝缘层选择性地去除第二硬掩模层。 在蚀刻过程中，第二硬掩模层和绝缘层之间的蚀刻速率的比可以在约100:1至约10,000:1的范围内。

    METHODS OF FABRICATING A SEMICONDUCTOR DEVICE WITH CAPACITORS USING MOLD STRUCTURE AND PROTECTION LAYER
    2.
    发明申请
    METHODS OF FABRICATING A SEMICONDUCTOR DEVICE WITH CAPACITORS USING MOLD STRUCTURE AND PROTECTION LAYER 有权
    使用模具结构和保护层制造具有电容器的半导体器件的方法

    公开(公告)号：US20140065784A1

    公开(公告)日：2014-03-06

    申请号：US13952207

    申请日：2013-07-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junho Yoon ,  Dongchan Kim ,  Gyungjin Min ,  Jaehong Park ,  Yongmoon Jang ,  Je-Woo Han

    IPC: H01L49/02

    CPC classification number: H01L28/40 ,  H01L28/90

    Abstract: A method of fabricating a semiconductor device with capacitors may include forming a mold structure on a lower structure, patterning the mold structure to form a plurality of holes exposing the lower structure, forming a protection layer on sidewalls of the mold structure exposed by the holes, forming lower electrodes in the holes provided with the protection layer, removing the mold structure to expose the protection layer, removing the protection layer to expose sidewalls of the lower electrodes, and sequentially forming a dielectric film and an upper electrode on the lower electrodes.

    Abstract translation: 制造具有电容器的半导体器件的方法可以包括在下部结构上形成模具结构，图案化模具结构以形成暴露下部结构的多个孔，在由孔露出的模具结构的侧壁上形成保护层， 在设置有保护层的孔中形成下电极，去除模具结构以露出​​保护层，去除保护层以暴露下电极的侧壁，并且在下电极上依次形成电介质膜和上电极。

    METHODS OF FORMING SEMICONDUCTOR DEVICES USING HARD MASKS
    5.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICES USING HARD MASKS 有权
    使用硬掩模形成半导体器件的方法

    公开(公告)号：US20150104947A1

    公开(公告)日：2015-04-16

    申请号：US14510331

    申请日：2014-10-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongchan Kim ,  Gyungjin Min ,  Minjoon Park ,  Seunghoon Park ,  KeunHee Bai ,  Kisoo Chang

    IPC: H01L21/308 ,  H01L21/306

    CPC classification number: H01L21/31111 ,  H01L21/31122 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/66795

    Abstract: Methods of forming a semiconductor device are provided. The methods may include forming an insulating layer including silicon on a substrate and sequentially forming a first hard mask layer and a second hard mask layer on the substrate. The first hard mask layer may include carbon, and the second hard mask layer may include carbon and impurities. The first and second hard mask layers may expose at least a portion of the insulating layer. The methods may also include performing an etching process to selectively remove the second hard mask layer with respect to the insulating layer. A ratio of etch rates between the second hard mask layer and the insulating layer during the etching process may be in a range of about 100:1 to about 10,000:1.

    Abstract translation: 提供了形成半导体器件的方法。 所述方法可以包括在衬底上形成包括硅的绝缘层，并且在衬底上依次形成第一硬掩模层和第二硬掩模层。 第一硬掩模层可以包括碳，第二硬掩模层可以包括碳和杂质。 第一和第二硬掩模层可以暴露绝缘层的至少一部分。 所述方法还可以包括执行蚀刻工艺以相对于绝缘层选择性地去除第二硬掩模层。 在蚀刻过程中，第二硬掩模层和绝缘层之间的蚀刻速率的比可以在约100:1至约10,000:1的范围内。

    Methods of fabricating a semiconductor device with capacitors using mold structure and protection layer
    6.
    发明授权
    Methods of fabricating a semiconductor device with capacitors using mold structure and protection layer 有权
    使用模具结构和保护层制造具有电容器的半导体器件的方法

    公开(公告)号：US08969167B2

    公开(公告)日：2015-03-03

    申请号：US13952207

    申请日：2013-07-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junho Yoon ,  Dongchan Kim ,  Gyungjin Min ,  Jaehong Park ,  Yongmoon Jang ,  Je-Woo Han

    IPC: H01L21/20 ,  H01L49/02

    CPC classification number: H01L28/40 ,  H01L28/90

    Abstract: A method of fabricating a semiconductor device with capacitors may include forming a mold structure on a lower structure, patterning the mold structure to form a plurality of holes exposing the lower structure, forming a protection layer on sidewalls of the mold structure exposed by the holes, forming lower electrodes in the holes provided with the protection layer, removing the mold structure to expose the protection layer, removing the protection layer to expose sidewalls of the lower electrodes, and sequentially forming a dielectric film and an upper electrode on the lower electrodes.

    Abstract translation: 制造具有电容器的半导体器件的方法可以包括在下部结构上形成模具结构，图案化模具结构以形成暴露下部结构的多个孔，在由孔露出的模具结构的侧壁上形成保护层， 在设置有保护层的孔中形成下电极，去除模具结构以露出​​保护层，去除保护层以暴露下电极的侧壁，并且在下电极上依次形成电介质膜和上电极。

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