公开(公告)号：US20240355678A1

公开(公告)日：2024-10-24

申请号：US18636463

申请日：2024-04-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Junyun Kweon ,  Haemin Park ,  Kwangyong Lee ,  Jesung Kim ,  Dayoung Cho

IPC: H01L21/78 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A semiconductor chip includes an active layer on a top surface of an underlying base substrate. The active layer has: bonding surface therein that delineates an interface between a bottom active layer and a top active layer extending on the bottom active layer, and a chamfered edge that extends entirely through the top active layer to fully expose a sidewall thereof but only partially through the bottom active layer, such that the chamfered edge has a vertical height greater than a thickness of the top active layer but less than a combined thickness of the top and bottom active layers. A protective layer is also provided, which covers at least a portion of a top surface of the active layer. A vertical level of a bottom of the chamfered edge may be higher than a vertical level of the top surface of the base substrate.

公开(公告)号：US20250125197A1

公开(公告)日：2025-04-17

申请号：US18884732

申请日：2024-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyun Kweon ,  Wooju Kim ,  Junho Yoon ,  Dayoung Cho ,  Jinwook Hong

IPC: H01L21/78 ,  B23K26/38 ,  B23K101/40 ,  H01L21/02 ,  H01L21/304 ,  H01L21/683

Abstract: A semiconductor chip includes a base substrate including a first surface, a second surface opposite to the first surface, and a sidewall extending between the first surface and the second surface, and a device layer on the first surface of the base substrate, wherein the base substrate includes a stress relief region within a first depth from the second surface and a second depth from the sidewall, and at least a portion of the sidewall of the base substrate is recessed inward from the sidewall of the device layer.