公开(公告)号：US12062626B2

公开(公告)日：2024-08-13

申请号：US18144902

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/544 ,  H01L2223/5446

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

公开(公告)号：US20230275037A1

公开(公告)日：2023-08-31

申请号：US18144902

申请日：2023-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/00 ,  H01L23/544 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L23/544 ,  H01L21/78 ,  H01L2223/5446

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

公开(公告)号：US11322405B2

公开(公告)日：2022-05-03

申请号：US16909136

申请日：2020-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Jungchul Lee ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim

IPC: G11B11/105 ,  B23K26/00 ,  B23K26/40 ,  H01L21/78 ,  H01L21/268 ,  H01L21/683 ,  H01L21/304

Abstract: According to an embodiment of inventive concepts, a substrate dicing method may include forming reformed patterns in a substrate using a laser beam, grinding a bottom surface of the substrate to thin the substrate, and expanding the substrate to divide the substrate into a plurality of semiconductor chips. The forming of the reformed patterns may include forming a first reformed pattern in the substrate and providing an edge focused beam to a region crossing the first reformed pattern to form a second reformed pattern in contact with the first reformed pattern.

公开(公告)号：US20220059472A1

公开(公告)日：2022-02-24

申请号：US17216279

申请日：2021-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

公开(公告)号：US20240178000A1

公开(公告)日：2024-05-30

申请号：US18519501

申请日：2023-11-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jesung Kim ,  Haemin Park ,  Heejae Nam ,  Junggeun Shin ,  Junho Yoon ,  Jungho Choi

IPC: H01L21/304 ,  B23K26/53 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L21/3043 ,  B23K26/53 ,  H01L21/6836 ,  H01L21/78 ,  B23K2101/40 ,  H01L2221/68327

Abstract: A wafer dicing method includes preparing a wafer having a plurality of device formation areas and a scribe lane area defining the plurality of device formation areas, forming a plurality of semiconductor devices in the plurality of device formation areas of the wafer, forming, in the scribe lane area, a plurality of first grooves partially passing through at least a portion of the wafer in a vertical direction, forming a plurality of second grooves by planarizing lower surfaces of the plurality of first grooves, forming one or more internal cracks in the wafer by radiating a laser beam along lower surfaces of the plurality of second grooves, and separating the plurality of semiconductor devices from each other along the one or more internal cracks.

公开(公告)号：US11676914B2

公开(公告)日：2023-06-13

申请号：US17216279

申请日：2021-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwayoung Lee ,  Heejae Nam ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim ,  Junho Yoon ,  Dongjin Lee

IPC: H01L23/544 ,  H01L23/00 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/544 ,  H01L2223/5446

Abstract: A semiconductor substrate may include a plurality of semiconductor chips and a protection pattern. The semiconductor chips may be divided by two scribe lanes intersecting each other. Corners of the semiconductor chips may be disposed at the intersection of the two scribe lanes. The protection pattern may be arranged at the intersection of the scribe lanes to surround the corners of the semiconductor chips. Thus, the corners of the semiconductor chips may be protected by the protection pattern form colliding with each other in a following grinding process.

公开(公告)号：US20240387460A1

公开(公告)日：2024-11-21

申请号：US18320553

申请日：2023-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heejae NAM ,  Junyun Kweon ,  Wooju Kim ,  Junggeun Shin

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package including a package substrate having an upper surface and a lower surface opposite to the upper surface, the package substrate having first substrate pads along a side portion thereof and second substrate pads outside the first substrate pads, being along the side portion, and arranged at positions higher than the first substrate pads, a first group of semiconductor chips sequentially stacked on the upper surface of the package substrate, and including at least one semiconductor chip, a second group of semiconductor chips sequentially stacked on the first group of semiconductor chips and including at least one semiconductor chip, first bonding wires electrically connecting chip pads of the first group of semiconductor chips to the first substrate pads, respectively, and second bonding wires electrically connecting chips pads of the second group of semiconductor chips to the second substrate pads, respectively may be provided.

公开(公告)号：US11854892B2

公开(公告)日：2023-12-26

申请号：US17699570

申请日：2022-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Jungchul Lee ,  Byungmoon Bae ,  Junggeun Shin ,  Hyunsu Sim

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/683 ,  H01L21/304

CPC classification number: H01L21/78 ,  H01L21/268 ,  H01L21/304 ,  H01L21/6836 ,  H01L2221/68336

Abstract: According to an embodiment of inventive concepts, a substrate dicing method may include forming reformed patterns in a substrate using a laser beam, grinding a bottom surface of the substrate to thin the substrate, and expanding the substrate to divide the substrate into a plurality of semiconductor chips. The forming of the reformed patterns may include forming a first reformed pattern in the substrate and providing an edge focused beam to a region crossing the first reformed pattern to form a second reformed pattern in contact with the first reformed pattern.

公开(公告)号：US20230082384A1

公开(公告)日：2023-03-16

申请号：US17730993

申请日：2022-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Yeongbeom Ko ,  Hwayoung Lee ,  Junggeun Shin ,  Hyunsu Sim ,  Kwangyong Lee ,  Jongho Lee

IPC: H01L21/67 ,  H01L21/683 ,  B23K26/53

Abstract: A substrate processing apparatus includes a chuck table including a mounting table having a mounting surface on which a substrate is mounted, wherein the mounting surface is a curved surface; and a laser supply head configured to irradiate the substrate attached to the mounting table with a laser beam.