公开(公告)号：US12015005B2

公开(公告)日：2024-06-18

申请号：US17537994

申请日：2021-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongbeom Ko ,  Wooju Kim ,  Heejae Nam ,  Jungseok Ryu ,  Haemin Park

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/32 ,  H01L25/0657 ,  H01L24/73 ,  H01L25/18 ,  H01L2224/32057 ,  H01L2224/32058 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2924/10156

Abstract: A semiconductor package includes a semiconductor chip on a substrate. The semiconductor chip includes an active region, and a scribe lane in continuity with an edge of the active region. A non-conductive film (NCF) is between the substrate and the semiconductor chip, the non-conductive film (NCF) at least partially defines a recess region overlapping with the scribe lane in plan view and extending on the active region.

公开(公告)号：US20240421140A1

公开(公告)日：2024-12-19

申请号：US18628182

申请日：2024-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Lee ,  Yeongbeom Ko ,  Seokgeun Ahn ,  Juhyeon Oh ,  Gwangjae Jeon

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor package includes a buffer die, a first core die stack stacked on the buffer die, the first core die stack including at least one first intermediate core and a first gap filling portion covering an outer surface of the at least one first intermediate core, and a second core die stack stacked on the first core die stack, the second core die stack including at least one second intermediate core and a second gap filling portion covering an outer surface of the at least one second intermediate core. The first gap filling portion and the second gap filling portion are directly bonded to each other.

公开(公告)号：US20250079249A1

公开(公告)日：2025-03-06

申请号：US18791760

申请日：2024-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeongbeom Ko ,  Kyounglim Suk ,  Jaegun Shin ,  Sanghoon Lee ,  Woojin Jang ,  Gwangjae Jeon

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L25/18

Abstract: A semiconductor package includes a buffer die, an intermediate core die stack on the buffer die, where the intermediate core die stack includes a plurality of intermediate core dies and a plurality of first gap filling portions that respectively overlap side surfaces of the plurality of intermediate core dies in a first direction, a top core die on the intermediate core die stack, and a second gap filling portion that overlaps side surfaces of the intermediate core die stack in the first direction and side surfaces of the top core die in the first direction.

公开(公告)号：US20240047296A1

公开(公告)日：2024-02-08

申请号：US18229824

申请日：2023-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongbeom Ko ,  Junyun Kweon ,  Wonil Seo

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3677 ,  H01L23/3128 ,  H01L24/16 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L25/18

Abstract: A semiconductor package includes a first semiconductor chip, a lower redistribution structure electrically connected to the first semiconductor chip, an upper redistribution structure on the first semiconductor chip, a conductive post electrically connecting the upper redistribution structure to the lower redistribution structure, and a first wire connecting a lower surface of the first semiconductor chip with an upper surface of the lower redistribution structure to dissipate heat of the first semiconductor chip.

公开(公告)号：US20230395547A1

公开(公告)日：2023-12-07

申请号：US18205329

申请日：2023-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyun Kweon ,  Yeongbeom Ko ,  Wooju Kim ,  Jungseok Ryu ,  Junho Yoon ,  Hwayoung Lee

IPC: H01L23/00 ,  H10B80/00

CPC classification number: H01L24/08 ,  H10B80/00 ,  H01L2224/08145

Abstract: A semiconductor device includes a first chip structure including a wiring structure disposed on a circuit elements, and first bonding metal layers and a first bonding insulating layer on the wiring structure, an upper surface of the first chip structure having an edge region and an inner region surrounded by the edge region, a second chip structure disposed on an inner region of the upper surface of the first chip structure, and including second bonding metal layers respectively bonded to the first bonding metal layers, a second bonding insulating layer bonded to the first bonding insulating layer, and a memory cell layer on the second bonding metal layers and the second bonding insulating layer, an insulating capping layer disposed on an upper surface of the second chip structure and extending to the edge region, and a connection pad disposed on a region of the insulating capping layer.

公开(公告)号：US20230082384A1

公开(公告)日：2023-03-16

申请号：US17730993

申请日：2022-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Yeongbeom Ko ,  Hwayoung Lee ,  Junggeun Shin ,  Hyunsu Sim ,  Kwangyong Lee ,  Jongho Lee

IPC: H01L21/67 ,  H01L21/683 ,  B23K26/53

Abstract: A substrate processing apparatus includes a chuck table including a mounting table having a mounting surface on which a substrate is mounted, wherein the mounting surface is a curved surface; and a laser supply head configured to irradiate the substrate attached to the mounting table with a laser beam.