公开(公告)号：US20200227289A1

公开(公告)日：2020-07-16

申请号：US16509815

申请日：2019-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Yoon Song ,  Chan-Hoon Park ,  Jong-Woo Sun ,  Jung-Mo Sung ,  Je-Woo Han ,  Jin-Young Park

IPC: H01L21/67 ,  H01J37/32

Abstract: In a plasma processing method, a substrate is loaded onto a lower electrode within a chamber. A plasma power is applied to form plasma within the chamber. A voltage function of a nonsinusoidal wave having a DC pulse portion and a ramp portion is generated. Generating the voltage function may include setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function in order to control an ion energy distribution generated at a surface of the substrate. A bias power of the nonsinusoidal wave is applied to the lower electrode.

公开(公告)号：US20140065784A1

公开(公告)日：2014-03-06

申请号：US13952207

申请日：2013-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Dongchan Kim ,  Gyungjin Min ,  Jaehong Park ,  Yongmoon Jang ,  Je-Woo Han

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L28/90

Abstract: A method of fabricating a semiconductor device with capacitors may include forming a mold structure on a lower structure, patterning the mold structure to form a plurality of holes exposing the lower structure, forming a protection layer on sidewalls of the mold structure exposed by the holes, forming lower electrodes in the holes provided with the protection layer, removing the mold structure to expose the protection layer, removing the protection layer to expose sidewalls of the lower electrodes, and sequentially forming a dielectric film and an upper electrode on the lower electrodes.

Abstract translation: 制造具有电容器的半导体器件的方法可以包括在下部结构上形成模具结构，图案化模具结构以形成暴露下部结构的多个孔，在由孔露出的模具结构的侧壁上形成保护层， 在设置有保护层的孔中形成下电极，去除模具结构以露出​​保护层，去除保护层以暴露下电极的侧壁，并且在下电极上依次形成电介质膜和上电极。

公开(公告)号：US11037806B2

公开(公告)日：2021-06-15

申请号：US16509815

申请日：2019-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Yoon Song ,  Chan-Hoon Park ,  Jong-Woo Sun ,  Jung-Mo Sung ,  Je-Woo Han ,  Jin-Young Park

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3065

Abstract: In a plasma processing method, a substrate is loaded onto a lower electrode within a chamber. A plasma power is applied to form plasma within the chamber. A voltage function of a nonsinusoidal wave having a DC pulse portion and a ramp portion is generated. Generating the voltage function may include setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function in order to control an ion energy distribution generated at a surface of the substrate. A bias power of the nonsinusoidal wave is applied to the lower electrode.

公开(公告)号：US09123657B2

公开(公告)日：2015-09-01

申请号：US14326960

申请日：2014-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjoon Park ,  Junho Yoon ,  Je-Woo Han ,  Chan-Won Kim

IPC: H01L21/76 ,  H01L21/308 ,  H01L49/02

CPC classification number: H01L21/3086 ,  H01L21/3085 ,  H01L21/31144 ,  H01L23/544 ,  H01L28/40 ,  H01L28/91 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device is provided. The method may include forming an interlayer insulating layer on a structure with a cell region and a peripheral circuit region, forming a first mask layer on the interlayer insulating layer, forming trenches in the first mask layer exposing the interlayer insulating layer by patterning the first mask layer on the peripheral circuit region, and forming key mask patterns in the trenches. An etch selectivity of the first mask patterns with respect to the interlayer insulating layer may be greater than that of the key mask patterns with respect to the interlayer insulating layer.

Abstract translation: 提供一种制造半导体器件的方法。 该方法可以包括在具有单元区域和外围电路区域的结构上形成层间绝缘层，在层间绝缘层上形成第一掩模层，在第一掩模层中形成沟槽，通过图案化第一掩模 并且在沟槽中形成键掩模图案。 第一掩模图案相对于层间绝缘层的蚀刻选择性可以大于键层掩模图案相对于层间绝缘层的蚀刻选择性。

公开(公告)号：US08969167B2

公开(公告)日：2015-03-03

申请号：US13952207

申请日：2013-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Dongchan Kim ,  Gyungjin Min ,  Jaehong Park ,  Yongmoon Jang ,  Je-Woo Han

IPC: H01L21/20 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01L28/90

Abstract: A method of fabricating a semiconductor device with capacitors may include forming a mold structure on a lower structure, patterning the mold structure to form a plurality of holes exposing the lower structure, forming a protection layer on sidewalls of the mold structure exposed by the holes, forming lower electrodes in the holes provided with the protection layer, removing the mold structure to expose the protection layer, removing the protection layer to expose sidewalls of the lower electrodes, and sequentially forming a dielectric film and an upper electrode on the lower electrodes.

Abstract translation: 制造具有电容器的半导体器件的方法可以包括在下部结构上形成模具结构，图案化模具结构以形成暴露下部结构的多个孔，在由孔露出的模具结构的侧壁上形成保护层， 在设置有保护层的孔中形成下电极，去除模具结构以露出​​保护层，去除保护层以暴露下电极的侧壁，并且在下电极上依次形成电介质膜和上电极。

公开(公告)号：US10892142B2

公开(公告)日：2021-01-12

申请号：US16182737

申请日：2018-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangjean Jeon ,  Jinyoung Park ,  Chanhoon Park ,  Hoyong Park ,  Jin Young Bang ,  JungHwan Um ,  Il Sup Choi ,  Je-Woo Han

IPC: H01J37/32 ,  H01L21/683

Abstract: A system for fabricating a semiconductor device may include a chamber, an electrostatic chuck used to load a substrate, a power source supplying an RF power to the electrostatic chuck, an impedance matcher between the power source and the electrostatic chuck, and a power transmission unit connecting the electrostatic chuck to the impedance matcher. The power transmission unit may include a power rod, which is connected to the electrostatic chuck and has a first outer diameter, and a coaxial cable. The coaxial cable may include an inner wire, an outer wire, and a dielectric material between the outer and inner wires. The inner wire connects the power rod to the impedance matcher and has a second outer diameter less than the first outer diameter. The outer wire is connected to the chamber and is provided to enclose the inner wire and has a first inner diameter less than the first outer diameter and greater than the second outer diameter. A ratio of the first inner diameter to the second outer diameter is greater than a dielectric constant of the dielectric material and less than three times the dielectric constant of the dielectric material.

公开(公告)号：US09812335B2

公开(公告)日：2017-11-07

申请号：US15066492

申请日：2016-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Woo Han ,  Junho Yoon ,  Kyohyeok Kim ,  Dongchan Kim ,  Sungyeon Kim ,  Jaehong Park ,  Jinyoung Park ,  KyungYub Jeon

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/31144 ,  H01L21/31116 ,  H01L21/76816

Abstract: A method of fabricating a semiconductor device is disclosed. The method may include forming an target layer on a substrate, forming a mask pattern on a target layer, performing a first process to etch the target layer and form a first sub-trench, and performing a second process to further etch the target layer and form a second sub-trench. First and second sidewall patterns may be formed on a sidewall of the mask pattern to be used as an etch mask in the first and second processes, respectively. Outer sidewalls of the first and second sidewall patterns may be formed to have different angles with respect to a top surface of the substrate.

公开(公告)号：US09647056B2

公开(公告)日：2017-05-09

申请号：US14961994

申请日：2015-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junho Yoon ,  Gyungjin Min ,  Jaehong Park ,  Yongmoon Jang ,  Je-Woo Han

IPC: H01L29/92 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L28/40 ,  H01L28/56 ,  H01L28/91 ,  H01L28/92

Abstract: Semiconductor devices are provided. Each of the semiconductor devices may include a plurality of electrodes. Moreover, each of the semiconductor devices may include a supporting pattern connected to sidewalls of the plurality of electrodes. Related methods of forming semiconductor devices are also provided. For example, the methods may include forming the supporting pattern before forming the plurality of electrodes.

公开(公告)号：US11521866B2

公开(公告)日：2022-12-06

申请号：US17198938

申请日：2021-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Yoon Song ,  Chan-Hoon Park ,  Jong-Woo Sun ,  Jung-Mo Sung ,  Je-Woo Han ,  Jin-Young Park

IPC: H01L21/67 ,  H01J37/32 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3065

Abstract: In a plasma processing method, a substrate is loaded onto a lower electrode within a chamber. A plasma power is applied to form plasma within the chamber. A voltage function of a nonsinusoidal wave having a DC pulse portion and a ramp portion is generated. Generating the voltage function may include setting a slope of the ramp portion and setting a duration ratio of the ramp portion to a cycle of the voltage function in order to control an ion energy distribution generated at a surface of the substrate. A bias power of the nonsinusoidal wave is applied to the lower electrode.

公开(公告)号：US09799561B2

公开(公告)日：2017-10-24

申请号：US15238836

申请日：2016-08-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Hoon Park ,  Dong-Chan Kim ,  Masayuki Tomoyasu ,  Je-Woo Han

IPC: H01L21/338 ,  H01L21/768 ,  H01L21/66 ,  H01L21/68 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/682 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L22/12 ,  H01L22/20 ,  H01L29/4983

Abstract: A method for fabricating a semiconductor device is disclosed. The method includes forming a first interlayer insulating layer including a first trench that is defined by a first gate spacer and a second trench that is defined by a second gate spacer on a substrate, forming a first gate electrode that fills a part of the first trench and a second gate electrode that fills a part of the second trench, forming a first capping pattern that fills the remainder of the first trench on the first gate electrode, forming a second capping pattern that fills the remainder of the second trench on the second gate electrode, forming a second interlayer insulating layer that covers the first gate spacer and the second gate spacer on the first interlayer insulating layer, forming a third interlayer insulating layer on the second interlayer insulating layer and forming a contact hole that penetrates the third interlayer insulating layer and the second interlayer insulating layer between the first gate electrode and the second gate electrode.