公开(公告)号：US20240237331A1

公开(公告)日：2024-07-11

申请号：US18350427

申请日：2023-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoin LEE ,  Byung-Hyun LEE ,  Hoouk LEE

IPC: H10B12/00 ,  H01L29/423

CPC classification number: H10B12/315 ,  H01L29/42356 ,  H10B12/03 ,  H10B12/482

Abstract: A semiconductor device includes a substrate including a cell array region and a core region disposed around the cell array region; a plurality of storage element contacts; a contact plug; and a contact plug spacer. The plurality of storage element contacts may include a first storage element contact and at least one second storage element contact, the first storage element contact is a closest storage element contact of the plurality of storage element contacts to the core region, such that the first storage element contact is between the core region and the at least one second storage element contact. A step difference in a vertical direction perpendicular to the substrate between a top surface of the first storage element contact and a top surface of the at least one second storage element contact is 5 nm or less.

公开(公告)号：US20240130111A1

公开(公告)日：2024-04-18

申请号：US18395918

申请日：2023-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Young CHOI ,  Seung Jin KIM ,  Byung-Hyun LEE ,  Sang Jae PARK

IPC: H10B12/00 ,  G11C5/10 ,  G11C11/402

CPC classification number: H10B12/34 ,  G11C5/10 ,  G11C11/4023 ,  H01L28/91

Abstract: A semiconductor device may comprise: a plurality of lower electrodes which are on a substrate; a first electrode support which is between adjacent lower electrodes and comprises a metallic material; a dielectric layer which is on the lower electrodes and the first electrode support to extend along profiles of the first electrode support and each of the lower electrodes; and an upper electrode which is on the dielectric layer.

公开(公告)号：US20210050221A1

公开(公告)日：2021-02-18

申请号：US16863244

申请日：2020-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjin KIM ,  Byung-Hyun LEE ,  Yoonyoung CHOI ,  Tae-Kyu KIM ,  Heesook CHEON ,  Bo-Wo CHOI ,  Hyun-Sil HONG

IPC: H01L21/311 ,  H01L21/48 ,  H01L21/027

Abstract: A method of fabricating a semiconductor device including preparing a substrate including a wafer inner region and a wafer edge region, the wafer inner region including a chip region and a scribe lane region, sequentially stacking a mold layer and a supporting layer on the substrate, forming a first mask layer on the supporting layer, the first mask layer including a first stepped region on the wafer edge region, forming a step-difference compensation pattern on the first stepped region, forming a second mask pattern including openings, on the first mask layer and the step-difference compensation pattern, and sequentially etching the first mask layer, the supporting layer, and the mold layer using the second mask pattern as an etch mask to form a plurality of holes in at least the mold layer may be provided.

公开(公告)号：US20150235947A1

公开(公告)日：2015-08-20

申请号：US14705416

申请日：2015-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung-Hyun LEE ,  Hoon LEE

IPC: H01L23/525 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5252 ,  G11C5/04 ,  G11C29/883 ,  H01L22/22 ,  H01L23/481 ,  H01L23/5256 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/32146 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01005 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.

Abstract translation: 提供了多芯片封装。 多芯片封装包括多个芯片，其包括至少一个坏芯片和至少一个堆叠好的芯片以及穿过芯片的多个穿通电极。 包含在所述至少一个坏芯片中的逻辑电路与所述多个穿透电极中的每一个绝缘。

公开(公告)号：US20240280895A1

公开(公告)日：2024-08-22

申请号：US18381773

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinnam YEEM ,  Hoin LEE ,  Dongkyun LEE ,  Sangchul YANG ,  Byung-Hyun LEE

IPC: G03F1/70 ,  H01L21/027

CPC classification number: G03F1/70 ,  H01L21/027 ,  H10B12/315

Abstract: A method of fabricating a semiconductor device may include forming a target pattern on a first wafer by performing a first exposure process, measuring a misalignment value of the target pattern, calculating a block misalignment value and a pattern misalignment value based on the misalignment value, calculating a block correction value based on the block misalignment value and calculating a pattern correction value based on the pattern misalignment value, and performing a second exposure process on a second wafer, based on the block correction value and the pattern correction value.

公开(公告)号：US20210159230A1

公开(公告)日：2021-05-27

申请号：US17032655

申请日：2020-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Young CHOI ,  Seung Jin KIM ,  Byung-Hyun LEE ,  Sang Jae PARK

IPC: H01L27/108 ,  G11C5/10 ,  H01L49/02 ,  G11C11/402

Abstract: A semiconductor device may comprise: a plurality of lower electrodes which are on a substrate; a first electrode support which is between adjacent lower electrodes and comprises a metallic material; a dielectric layer which is on the lower electrodes and the first electrode support to extend along profiles of the first electrode support and each of the lower electrodes; and an upper electrode which is on the dielectric layer.