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    INDUCTOR AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    INDUCTOR AND MANUFACTURING METHOD THEREOF 审中-公开
    电感器及其制造方法

    公开(公告)号：US20140176278A1

    公开(公告)日：2014-06-26

    申请号：US13841107

    申请日：2013-03-15

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Dong Hwan LEE ,  Seung Wook PARK ,  Christian ROMERO ,  Young Do KWEON ,  Jin Gu KIM

    IPC: H01F27/29 ,  H01F41/02

    CPC classification number: H01F27/2828 ,  H01F27/292 ,  H01F41/10 ,  H01F2017/048 ,  Y10T29/49073

    Abstract: There is provided an inductor, including a circuit board having an input and output terminal formed on a lower surface thereof, a connection pad formed on an upper surface thereof, and a via electrically connecting the input and output terminal and the connection pad, a coil having both ends joined to the connection pad and wound in a circular or a polygonal spiral shape in a longitudinal direction of the circuit board so as to have one or more turns, and a body stacked on the circuit board such that the coil and the connection pad are embedded therein.

    Abstract translation: 提供一种电感器，包括电路板，其电路板具有形成在其下表面上的输入和输出端子，形成在其上表面上的连接焊盘和将输入和输出端子与连接焊盘电连接的通孔，线圈 其两端连接到连接焊盘，并沿着电路板的纵向缠绕成圆形或多边形螺旋形，以便具有一个或多个匝，以及堆叠在电路板上的主体，使得线圈和连接 垫嵌入其中。

    COPPER CLAD LAMINATE AND METHOD FOR MANUFACTURING THE SAME
    2.
    发明申请
    COPPER CLAD LAMINATE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    铜箔层压板及其制造方法

    公开(公告)号：US20150230335A1

    公开(公告)日：2015-08-13

    申请号：US14618681

    申请日：2015-02-10

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Kwang Jik LEE ,  Jin Gu KIM ,  Myung Jae YOO ,  Ichiro OGURA ,  Hye Suk SHIN

    IPC: H05K1/05 ,  H05K3/38 ,  H05K1/03

    CPC classification number: H05K1/0373 ,  H05K1/0366 ,  H05K3/022 ,  H05K3/381 ,  H05K2201/0209 ,  H05K2201/0233 ,  Y10T428/2495 ,  Y10T428/31678

    Abstract: Embodiments of the invention provide a copper clad laminate, and more particularly, to a copper clad laminate and a method for manufacturing the same capable of increasing a peel strength by adding a stress relaxation filler to an insulating layer of a copper clad laminate, along with an inorganic filler. To improve an adhesion of a substrate, the stress relaxation filler is distributed into the resin, along with the inorganic filler, and is entirely distributed into the varnish, and is more effectively added to the vicinity of a bonded interface between the insulating layer and the copper clad layer, thereby improving the overall adhesion.

    Abstract translation: 本发明的实施方案提供一种覆铜层压板，更具体地说，涉及覆铜层压板及其制造方法，其能够通过向覆铜层压板的绝缘层添加应力松弛填料而提高剥离强度，以及 无机填料。 为了提高基材的粘附性，应力松弛填料与无机填料一起分配到树脂中，并且完全分散在清漆中，并且更有效地添加到绝缘层和绝缘层之间的键合界面附近 铜包覆层，从而提高整体粘合性。

    FAN-OUT SEMICONDUCTOR PACKAGE
    5.
    发明申请
    FAN-OUT SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190019757A1

    公开(公告)日：2019-01-17

    申请号：US15819541

    申请日：2017-11-21

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Ji Hyun LEE ,  Jin Gu KIM ,  Chang Bae LEE ,  Jin Su KIM

    IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00

    Abstract: A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the semiconductor chip and including a first redistribution layer electrically connected to the connection pads and a second redistribution layer electrically connected to the connection pads and disposed on the first redistribution layer. The first redistribution layer includes a first pattern having a plurality of degassing holes, the second redistribution layer includes a second pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width greater than the first line width, and the second line portion overlaps at least one of the plurality of degassing holes when being projected in a direction perpendicular to the active surface.

    SEMICONDUCTOR PACKAGE
    8.
    发明申请
    SEMICONDUCTOR PACKAGE 审中-公开

    公开(公告)号：US20190122994A1

    公开(公告)日：2019-04-25

    申请号：US15950000

    申请日：2018-04-10

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Yong Koon LEE ,  Jin Gu KIM ,  Jin Su KIM

    IPC: H01L23/552 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

    Abstract: A semiconductor package includes a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least a portion of the semiconductor chip; and a connection member including an insulating layer disposed on the active surface of the semiconductor chip, a signal pattern disposed in the insulating layer, first ground patterns disposed to be spaced apart from the signal pattern on both sides of the signal pattern, second ground patterns disposed to be spaced apart from the signal pattern in an upper portion and a lower portion of the signal pattern, and line vias connecting the first ground patterns and the second ground patterns to each other and having a line shape.

    PRINTED CIRCUIT BOARD AND METHOD OF FABRICATING THE SAME
    9.
    发明申请
    PRINTED CIRCUIT BOARD AND METHOD OF FABRICATING THE SAME 审中-公开
    印刷电路板及其制造方法

    公开(公告)号：US20150000958A1

    公开(公告)日：2015-01-01

    申请号：US14074338

    申请日：2013-11-07

    Applicant: Samsung Electro-Mechanics Co., Ltd.

    Inventor： Kyoung Moo HARR ,  Hyung Jin JEON ,  Jin Gu KIM ,  Young Jae LEE ,  Young Do KWEON ,  Chang Bae LEE

    IPC: H05K1/02 ,  H05K3/46 ,  H05K3/00

    CPC classification number: H05K3/4647 ,  H05K2201/09827

    Abstract: The present invention discloses a printed circuit board including a lower wiring layer, an insulating layer which buries the lower wiring layer, and an upper wiring layer formed on the insulating layer to improve reliability of interlayer electrical connection between the wiring layers, wherein the interlayer connection between the upper wiring layer and the lower wiring layer is performed by a via electrode which is provided between the upper wiring layer and the lower wiring layer and has an upper surface bonded to the upper wiring layer and a lower surface bonded to the lower wiring layer, wherein the lower surface of the via electrode is larger than the upper surface thereof.

    Abstract translation: 本发明公开了一种印刷电路板，包括下布线层，埋置下布线层的绝缘层和形成在绝缘层上的上布线层，以提高布线层之间的层间电连接的可靠性，其中层间连接 上布线层和下布线层之间的通孔电极通过设置在上布线层和下布线层之间的通孔电极进行，并且具有与上布线层接合的上表面和接合到下布线层的下表面 其中，所述通孔电极的下表面大于其上表面。

    PRINTED CIRCUIT BOARD AND SURFACE TREATMENT METHOD OF PRINTED CIRCUIT BOARD
    10.
    发明申请
    PRINTED CIRCUIT BOARD AND SURFACE TREATMENT METHOD OF PRINTED CIRCUIT BOARD 审中-公开
    印刷电路板和印刷电路板的表面处理方法

    公开(公告)号：US20140182905A1

    公开(公告)日：2014-07-03

    申请号：US14143475

    申请日：2013-12-30

    Applicant: Samsung Electro-Mechanics Co., Ltd.

    Inventor： Kyung Moo HAR ,  Chang Bae LEE ,  Jin Gu KIM ,  Young Do KWEON

    IPC: H05K13/00 ,  H05K1/09

    CPC classification number: H05K1/09 ,  H05K3/247 ,  H05K3/3484 ,  H05K2201/0376 ,  H05K2201/09472 ,  H05K2203/043 ,  H05K2203/0557 ,  H05K2203/081

    Abstract: Disclosed herein are a printed circuit board including a copper foil layer surface treated with Pb-free solder having the same height as that of a solder resist, and a surface treatment method of the printed circuit board.According to the present invention, the surface treatment of the package board or interposer board having an ultra-fine pitch (300 μm or less) may be easily implemented by a cheap process. In addition, the surface treatment of the printed circuit board may be eco-friendly performed by using the Pb-free solder, and it may be easy to surface treat the package board or interposer board based on the organic material sensitive to a high temperature.

    Abstract translation: 本发明公开了一种印刷电路板，其包括利用与阻焊剂相同高度的无铅焊料处理的铜箔层表面和印刷电路板的表面处理方法。 根据本发明，可以通过廉价的处理容易地实现具有超细间距（300μm以下）的封装基板或中介板的表面处理。 此外，印刷电路板的表面处理可以通过使用无铅焊料进行环保处理，并且可以容易地基于对高温敏感的有机材料来表面处理封装板或插入板。

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