公开(公告)号：US20140327149A1

公开(公告)日：2014-11-06

申请号：US14333110

申请日：2014-07-16

Applicant: John S. Guzek ,  Ravi K. Nalla ,  Javier Solo Gonzalez ,  Drew Delaney ,  Suresh Pothukuchi ,  Mohit Mamodia ,  Edward Zarbock ,  Johanna M. Swan

Inventor： John S. Guzek ,  Ravi K. Nalla ,  Javier Solo Gonzalez ,  Drew Delaney ,  Suresh Pothukuchi ,  Mohit Mamodia ,  Edward Zarbock ,  Johanna M. Swan

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/48137 ,  H01L2224/48472 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.

Abstract translation: 一种装置包括具有与无芯基板成一体的贯通硅通孔（TSV）嵌入管芯的无芯基板。 该设备包括连接到TSV管芯并且设置在无芯基板之上的后续管芯。

公开(公告)号：US20120074581A1

公开(公告)日：2012-03-29

申请号：US12890082

申请日：2010-09-24

Applicant: John S. Guzek ,  Ravi K. Nalla ,  Javier Soto Gonzalez ,  Drew Delaney ,  Suresh Pothukuchi ,  Mohit Mamodia ,  Edward Zarbock ,  Johanna M. Swan

Inventor： John S. Guzek ,  Ravi K. Nalla ,  Javier Soto Gonzalez ,  Drew Delaney ,  Suresh Pothukuchi ,  Mohit Mamodia ,  Edward Zarbock ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L21/50

CPC classification number: H01L23/5384 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/48137 ,  H01L2224/48472 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.

Abstract translation: 一种装置包括具有与无芯基板成一体的贯通硅通孔（TSV）嵌入管芯的无芯基板。 该设备包括连接到TSV管芯并且设置在无芯基板之上的后续管芯。

公开(公告)号：US20110241186A1

公开(公告)日：2011-10-06

申请号：US12755201

申请日：2010-04-06

Applicant: Ravi K. Nalla ,  Drew Delaney

Inventor： Ravi K. Nalla ,  Drew Delaney

IPC: H01L23/552 ,  H01L21/50 ,  H01L21/58

CPC classification number: H01L23/585 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68345 ,  H01L2224/12105 ,  H01L2224/13021 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/14 ,  H01L2924/1815 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括在载体材料中形成空腔，将模具附接在空腔中，其中模具的背面包括填充金属的DBF，在模具附近形成介电材料并在载体材料的底侧上形成 通过在电介质材料上建立层，以及从无芯基板去除载体材料，从而形成无芯基板。

公开(公告)号：US20140295621A1

公开(公告)日：2014-10-02

申请号：US14305439

申请日：2014-06-16

Applicant: John S. Guzek ,  Ravi K. Nalla ,  Javier Solo Gonzalez ,  Drew Delaney ,  Suresh Pothukuchi ,  Mohit Mamodia ,  Edward Zarbock ,  Johanna M. Swan

Inventor： John S. Guzek ,  Ravi K. Nalla ,  Javier Solo Gonzalez ,  Drew Delaney ,  Suresh Pothukuchi ,  Mohit Mamodia ,  Edward Zarbock ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/48137 ,  H01L2224/48472 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.

公开(公告)号：US08786066B2

公开(公告)日：2014-07-22

申请号：US12890082

申请日：2010-09-24

Applicant: John S. Guzek ,  Ravi K. Nalla ,  Javier Soto Gonzalez ,  Drew Delaney ,  Suresh Pothukuchi ,  Mohit Mamodia ,  Edward Zarbock ,  Johanna M. Swan

Inventor： John S. Guzek ,  Ravi K. Nalla ,  Javier Soto Gonzalez ,  Drew Delaney ,  Suresh Pothukuchi ,  Mohit Mamodia ,  Edward Zarbock ,  Johanna M. Swan

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/48137 ,  H01L2224/48472 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.

Abstract translation: 一种装置包括具有与无芯基板成一体的贯通硅通孔（TSV）嵌入管芯的无芯基板。 该设备包括连接到TSV管芯并且设置在无芯基板之上的后续管芯。

公开(公告)号：US20110316140A1

公开(公告)日：2011-12-29

申请号：US12825729

申请日：2010-06-29

Applicant: Ravi K. Nalla ,  Mathew J. Manusharow ,  Drew Delaney

Inventor： Ravi K. Nalla ,  Mathew J. Manusharow ,  Drew Delaney

IPC: H01L23/538 ,  H01L21/60 ,  H01L23/48

CPC classification number: H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/82105 ,  H01L2224/82106 ,  H01L2224/83203 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic package includes a substrate (110), a die (120) embedded within the substrate, the die having a front side (121) and a back side (122) and a through-silicon-via (123) therein, build-up layers (130) built up over the front side of the die, and a power plane (140) in physical contact with the back side of the die. In another embodiment, the microelectronic package comprises a substrate (210), a first die (220) and a second die (260) embedded in the substrate and having a front side (221, 261) and a back side (222, 262) and a through-silicon-via (223, 263) therein, build-up layers (230) over the front sides of the first and second dies, and an electrically conductive structure (240) in physical contact with the back sides of the first and second dies.

Abstract translation: 微电子封装包括衬底（110），嵌入衬底内的管芯（120），管芯具有前侧（121）和后侧（122）以及贯通硅通孔（123） 在模具的前侧构建的上层（130）和与模具的背面物理接触的动力平面（140）。 在另一个实施例中，微电子封装包括衬底（210），嵌入衬底中的第一裸片（220）和第二裸片（260），并具有正面（221,261）和背面（222,262） 和其中的穿硅通孔（223,263），在第一和第二模具的前侧上方的堆积层（230），以及与第一和第二模具的背面物理接触的导电结构（240） 和第二个死亡。

公开(公告)号：US20110254124A1

公开(公告)日：2011-10-20

申请号：US12761782

申请日：2010-04-16

Applicant: Ravi K. Nalla ,  John Guzek ,  Javier Soto Gonzalez ,  Drew Delaney ,  Hamid Azimi

Inventor： Ravi K. Nalla ,  John Guzek ,  Javier Soto Gonzalez ,  Drew Delaney ,  Hamid Azimi

IPC: H01L27/08 ,  H01L23/552 ,  B32B38/10

CPC classification number: H01L23/49822 ,  H01L21/02109 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76897 ,  H01L23/4824 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/552 ,  H01L23/645 ,  H01L24/19 ,  H01L24/20 ,  H01L25/16 ,  H01L2221/68359 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/1206 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/185 ,  H05K3/4682 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, wherein the carrier material comprises a top layer and a bottom layer separated by an etch stop layer; forming a dielectric material adjacent the die, forming a coreless substrate by building up layers on the dielectric material, and then removing the top layer carrier material and etch stop layer from the bottom layer carrier material.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将管芯附接到载体材料，其中载体材料包括由蚀刻停止层分隔的顶层和底层; 在模具附近形成电介质材料，通过在电介质材料上形成层而形成无芯衬底，然后去除顶层载体材料并从底层载体材料蚀刻停止层。

公开(公告)号：US20140367843A1

公开(公告)日：2014-12-18

申请号：US14293222

申请日：2014-06-02

Applicant: Ravi K. Nalla ,  Mathew J. Manusharow

Inventor： Ravi K. Nalla ,  Mathew J. Manusharow

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L23/36

CPC classification number: H01L24/20 ,  H01L21/568 ,  H01L21/768 ,  H01L23/3107 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/12105 ,  H01L2224/13021 ,  H01L2224/2101 ,  H01L2224/221 ,  H01L2224/24227 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H05K1/0209 ,  H05K1/185 ,  H05K3/4682

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括将管芯附接到载体材料，形成围绕管芯的电介质材料，在电介质材料中形成堆积层，以形成无芯无阻堆积的封装结构，以及图案化载体材料以在封装结构上形成微通道结构。

公开(公告)号：US20130344662A1

公开(公告)日：2013-12-26

申请号：US13934522

申请日：2013-07-03

Applicant: Mathew J. Manusharow ,  Mark S Hlad ,  Ravi K. Nalla

Inventor： Mathew J. Manusharow ,  Mark S Hlad ,  Ravi K. Nalla

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/3511 ,  H05K1/183 ,  H05K3/4641 ,  H01L2924/00

Abstract: A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure.

Abstract translation: 一种结构包括用于支撑半导体器件的混合衬底，该半导体器件包括其中嵌入半导体器件的无凸起积聚层和层叠芯结构。 通过与层压芯结构中的电镀通孔连接的无刷构建层结构的后续接合焊盘的加强电镀将无凸起的堆积层和层叠芯结构作为一体的装置。

公开(公告)号：US08580616B2

公开(公告)日：2013-11-12

申请号：US13629931

申请日：2012-09-28

Applicant: Ravi K. Nalla ,  Mathew J. Manusharow ,  Pramod Malatkar

Inventor： Ravi K. Nalla ,  Mathew J. Manusharow ,  Pramod Malatkar

IPC: H01L21/00

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L24/93 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/20 ,  H01L2224/21 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/22 ,  H01L2224/2201 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/251 ,  H01L2224/25105 ,  H01L2224/2518 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/821 ,  H01L2224/82101 ,  H01L2224/82106 ,  H01L2224/93 ,  H01L2225/06524 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/82 ,  H01L2221/68304 ,  H01L2924/00

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include a die embedded in a coreless substrate, wherein a mold compound surrounds the die, and wherein the die comprises TSV connections on a first side and C4 pads on a second side of the die, a dielectric material on a first side and on a second side of the mold compound; and interconnect structures coupled to the C4 pads and to the TSV pads. Embodiments further include forming packaging structures wherein multiple dies are fully embedded within a BBUL package without PoP lands.

Abstract translation: 描述了形成微电子封装结构的方法及由此形成的相关结构。 这些方法可以包括嵌入在无芯基板中的模具，其中模具化合物围绕模头，并且其中模具包括在第一侧上的TSV连接和在模具的第二侧上的C4焊盘，在第一侧上的电介质材料， 在模具化合物的第二面上; 以及耦合到所述C4焊盘和所述TSV焊盘的互连结构。 实施例还包括形成其中多个管芯完全嵌入BBUL封装中而不具有PoP焊盘的封装结构。