公开(公告)号：US20180040478A1

公开(公告)日：2018-02-08

申请号：US15723352

申请日：2017-10-03

Applicant: Renesas Electronics Corporation

Inventor： Yusuke TERADA ,  Shigeya TOYOKAWA ,  Atsushi MAEDA

IPC: H01L21/02 ,  G02F1/1343 ,  G02F1/1362 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/762 ,  G02F1/1333 ,  H01L29/66 ,  H01L27/12 ,  G02F1/1368 ,  G02F1/133

CPC classification number: H01L21/02274 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/136295 ,  H01L21/31051 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76837 ,  H01L21/76895 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/50 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/088 ,  H01L27/124 ,  H01L29/0653 ,  H01L29/66477 ,  H01L29/6675 ,  H01L29/78 ,  H01L29/7836 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

公开(公告)号：US20170117143A1

公开(公告)日：2017-04-27

申请号：US15397800

申请日：2017-01-04

Applicant: Renesas Electronics Corporation

Inventor： Yusuke TERADA ,  Shigeya TOYOKAWA ,  Atsushi MAEDA

IPC: H01L21/02 ,  H01L21/762 ,  G02F1/1362 ,  H01L29/66 ,  G02F1/1333 ,  G02F1/1343 ,  H01L21/768 ,  H01L21/3105

CPC classification number: H01L21/02274 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/136295 ,  H01L21/31051 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76837 ,  H01L21/76895 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/50 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/088 ,  H01L27/124 ,  H01L29/0653 ,  H01L29/66477 ,  H01L29/6675 ,  H01L29/78 ,  H01L29/7836 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

公开(公告)号：US20150311220A1

公开(公告)日：2015-10-29

申请号：US14679056

申请日：2015-04-06

Applicant: Renesas Electronics Corporation

Inventor： Shigeya TOYOKAWA ,  Michimoto KAMINAGA ,  Kentaro YAMADA

IPC: H01L27/115 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  G11C16/12 ,  H01L21/02 ,  H01L21/28 ,  G11C16/14 ,  G11C16/08 ,  G11C16/26 ,  H01L29/788 ,  H01L21/311

CPC classification number: G11C16/12 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11558 ,  H01L29/7883

Abstract: To enhance the write speed of a nonvolatile memory. A charge injection/emission part of a nonvolatile memory cell includes an active region having an upper face, a side wall, and a shoulder part connecting the upper face and the side wall, a conductor film covering the upper face and the shoulder part of the active region, and a capacitance insulating film provided between the conductor film and the active region. Furthermore, the active region has a protrusion part constituted of a first concave part with respect to the upper face and a second concave part with respect to the side wall, in the shoulder part.

Abstract translation: 提高非易失性存储器的写入速度。 非易失性存储单元的电荷注入/发射部分包括具有上表面，侧壁和连接上表面和侧壁的肩部的有源区，覆盖上表面和侧壁的上表面和肩部的导体膜 有源区和设置在导体膜和有源区之间的电容绝缘膜。 此外，有源区具有在肩部中由相对于上表面的第一凹部和相对于侧壁的第二凹部构成的突出部。

公开(公告)号：US20180315673A1

公开(公告)日：2018-11-01

申请号：US15954121

申请日：2018-04-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shigeya TOYOKAWA ,  Shuhei YAMAGUCHI ,  Koji HASEGAWA

IPC: H01L21/66 ,  H01L21/28 ,  H01L29/423

Abstract: A semiconductor chip has an evaluation pattern that is included in a monitor pattern. This evaluation pattern is constituted by a first pattern and a second pattern opposite to each other in an X direction. Further, the first pattern is constituted by a convex shape protruding in a direction away from the second pattern in the X direction.

公开(公告)号：US20140051219A1

公开(公告)日：2014-02-20

申请号：US14060464

申请日：2013-10-22

Applicant: Renesas Electronics Corporation

Inventor： Yusuke TERADA ,  Shigeya TOYOKAWA ,  Atsushi MAEDA

IPC: H01L29/66

CPC classification number: H01L21/02274 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/136295 ,  H01L21/31051 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76837 ,  H01L21/76895 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/50 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/088 ,  H01L27/124 ,  H01L29/0653 ,  H01L29/66477 ,  H01L29/6675 ,  H01L29/78 ,  H01L29/7836 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

Abstract translation: 在LCD驱动器中，在高耐压MISFET中，栅电极的端部运行到电场松弛绝缘区域上。 在高电压MISFET的第一层的层间绝缘膜上形成用于成为源极线或漏极线的电线。 此时，当从半导体衬底和栅极绝缘膜之间的界面到栅电极的上部的距离定义为“a”，并且从栅电极的上部到上部的距离 其上形成有导线的层间绝缘膜被定义为“b”，建立a> b的关系。 在以这种方式构成的这种高耐压MISFET中，布线布置成不与高电压MISFET的栅电极平面地重叠。