公开(公告)号：US20180040478A1

公开(公告)日：2018-02-08

申请号：US15723352

申请日：2017-10-03

Applicant: Renesas Electronics Corporation

Inventor： Yusuke TERADA ,  Shigeya TOYOKAWA ,  Atsushi MAEDA

IPC: H01L21/02 ,  G02F1/1343 ,  G02F1/1362 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/762 ,  G02F1/1333 ,  H01L29/66 ,  H01L27/12 ,  G02F1/1368 ,  G02F1/133

CPC classification number: H01L21/02274 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/136295 ,  H01L21/31051 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76837 ,  H01L21/76895 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/50 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/088 ,  H01L27/124 ,  H01L29/0653 ,  H01L29/66477 ,  H01L29/6675 ,  H01L29/78 ,  H01L29/7836 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

公开(公告)号：US20170117143A1

公开(公告)日：2017-04-27

申请号：US15397800

申请日：2017-01-04

Applicant: Renesas Electronics Corporation

Inventor： Yusuke TERADA ,  Shigeya TOYOKAWA ,  Atsushi MAEDA

IPC: H01L21/02 ,  H01L21/762 ,  G02F1/1362 ,  H01L29/66 ,  G02F1/1333 ,  G02F1/1343 ,  H01L21/768 ,  H01L21/3105

CPC classification number: H01L21/02274 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/136295 ,  H01L21/31051 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76837 ,  H01L21/76895 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/50 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/088 ,  H01L27/124 ,  H01L29/0653 ,  H01L29/66477 ,  H01L29/6675 ,  H01L29/78 ,  H01L29/7836 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

公开(公告)号：US20140051219A1

公开(公告)日：2014-02-20

申请号：US14060464

申请日：2013-10-22

Applicant: Renesas Electronics Corporation

Inventor： Yusuke TERADA ,  Shigeya TOYOKAWA ,  Atsushi MAEDA

IPC: H01L29/66

CPC classification number: H01L21/02274 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/136295 ,  H01L21/31051 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76837 ,  H01L21/76895 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/50 ,  H01L23/53295 ,  H01L23/535 ,  H01L27/088 ,  H01L27/124 ,  H01L29/0653 ,  H01L29/66477 ,  H01L29/6675 ,  H01L29/78 ,  H01L29/7836 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

Abstract translation: 在LCD驱动器中，在高耐压MISFET中，栅电极的端部运行到电场松弛绝缘区域上。 在高电压MISFET的第一层的层间绝缘膜上形成用于成为源极线或漏极线的电线。 此时，当从半导体衬底和栅极绝缘膜之间的界面到栅电极的上部的距离定义为“a”，并且从栅电极的上部到上部的距离 其上形成有导线的层间绝缘膜被定义为“b”，建立a> b的关系。 在以这种方式构成的这种高耐压MISFET中，布线布置成不与高电压MISFET的栅电极平面地重叠。