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公开(公告)号：US20180315673A1
公开(公告)日：2018-11-01
申请号：US15954121
申请日：2018-04-16
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Shigeya TOYOKAWA , Shuhei YAMAGUCHI , Koji HASEGAWA
IPC: H01L21/66 , H01L21/28 , H01L29/423
Abstract: A semiconductor chip has an evaluation pattern that is included in a monitor pattern. This evaluation pattern is constituted by a first pattern and a second pattern opposite to each other in an X direction. Further, the first pattern is constituted by a convex shape protruding in a direction away from the second pattern in the X direction.
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