公开(公告)号：US20180331210A1

公开(公告)日：2018-11-15

申请号：US15912099

申请日：2018-03-05

Applicant: Renesas Electronics Corporation

Inventor： Kazuhisa MORI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L27/06 ,  H01L23/495 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L21/823437 ,  H01L21/823456 ,  H01L23/4951 ,  H01L23/49562 ,  H01L23/49575 ,  H01L27/0629 ,  H01L27/0716 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/4238 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/49113 ,  H01L2924/00014

Abstract: A semiconductor device with a simplified structure including an energization control element and reverse coupling protection element, and a manufacturing method therefor. Its semiconductor substrate has deep and shallow trenches in its first surface. A first n-type impurity region lies in its second surface in contact with the deep trench bottom. A p-type impurity region includes: a p-type base region to make a pn junction with the first n-type region and in contact with the shallow trench bottom; and a back gate region joined to the p-type base region, lying in the first surface. A second n-type impurity region makes a pn junction with the p-type impurity region, lying in the first surface in contact with the shallow trench side face. An n+ source region makes a pn junction with the p-type region, lying in the first surface in contact with the side faces of deep and shallow trenches.

公开(公告)号：US20240162222A1

公开(公告)日：2024-05-16

申请号：US18509870

申请日：2023-11-15

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA ,  Hideki NIWAYAMA ,  Hiroyoshi KUDOU ,  Kazuhisa MORI ,  Kodai WADA

IPC: H01L27/06 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/823885 ,  H01L21/823892 ,  H01L28/20 ,  H01L29/063 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66734 ,  H01L29/7813

Abstract: Reliability of a semiconductor device is improved and reduction in yield is reduced. In a semiconductor substrate SUB, a trench TR is formed. A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. In the semiconductor substrate SUB, a body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. The source region NS, the n-type source region, the n-type drain region, the p-type source region and the p-type drain region are subjected to heat treatment. After heat treatment, a p-type column region PC is formed in the semiconductor substrate SUB located below the body region PB.

公开(公告)号：US20240162143A1

公开(公告)日：2024-05-16

申请号：US18509874

申请日：2023-11-15

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA ,  Hideki NIWAYAMA ,  Hiroyoshi KUDOU ,  Kazuhisa MORI ,  Kodai WADA

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/76877 ,  H01L21/76885 ,  H01L27/088 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a semiconductor substrate SUB, a trench TR is formed.
A gate-electrode GE1 is formed inside the trench TR via a gate insulating film GI1. A body region PB, a well region PW1 and a well region NW1 are formed. A source-region NS is formed in the body-region PB. In the well region PW1, an n-type source region and an n-type drain region are formed. In the well region NW1, a p-type source region and a p-type drain region are formed. An interlayer insulating film IL1 is formed on the upper surface of semiconductor substrate SUB. In the interlayer insulating film IL1, a hole CH1 is formed in the source region NS and in the body region PB. Holes CH3 are formed in the interlayer insulating film IL1 so as to reach the n-type source region, the n-type drain region, the p-type source region and the p-type drain region.

公开(公告)号：US20250015175A1

公开(公告)日：2025-01-09

申请号：US18890208

申请日：2024-09-19

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori KAYA ,  Katsumi EIKYU ,  Akihiro SHIMOMURA ,  Hiroshi YANAGIGAWA ,  Kazuhisa MORI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.

公开(公告)号：US20230291401A1

公开(公告)日：2023-09-14

申请号：US18059615

申请日：2022-11-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuhisa MORI ,  Toshiyuki HATA

IPC: H03K17/687 ,  H01L23/00 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/739 ,  H01L23/498

CPC classification number: H03K17/6871 ,  H01L23/49811 ,  H01L24/13 ,  H01L24/48 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7397 ,  H01L29/7813 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/73265 ,  H01L2924/182 ,  H01L2924/1811 ,  H01L2924/13091

Abstract: Performance of a semiconductor device is enhanced. A loss of a circuit device using a semiconductor device as a switch is reduced. A semiconductor device includes: a first semiconductor chip having a first MOSFET of p-type and a first parasitic diode; and a second semiconductor chip having a second MOSFET of n-type and a second parasitic diode. On front surfaces of the first and second semiconductor chips, a first source electrode and a first gate wiring and a second source electrode and a second gate wiring are formed, respectively. On back surfaces of the first and second semiconductor chips, first and second drain electrodes are formed, respectively. The second back surface and the first front surface face each other such that the second drain electrode and the first source electrode come into contact with each other via a conductive paste.

公开(公告)号：US20240243198A1

公开(公告)日：2024-07-18

申请号：US18407125

申请日：2024-01-08

Applicant: Renesas Electronics Corporation

Inventor： Hiroshi YANAGIGAWA ,  Yasutaka NAKASHIBA ,  Kazuhisa MORI ,  Koichi HASEGAWA

IPC: H01L29/78 ,  G01K7/01 ,  H01L23/00 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7813 ,  G01K7/01 ,  H01L24/45 ,  H01L24/48 ,  H01L29/0696 ,  H01L29/66734 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48464 ,  H01L2224/48472 ,  H01L2924/13091

Abstract: According to this present application, a reliability of a semiconductor device can be improved. The semiconductor device has a first region where a MOSFET is formed, and a second region where a temperature sensor transistor is formed. A body region is formed in a semiconductor substrate of the first region, and a base region is formed in the semiconductor substrate of the second region. A source region is formed in the body region and an emitter region is formed in the base region. A first column region is formed in the semiconductor substrate located below the body region, and a second column region is formed in the semiconductor substrate located below the base region.

公开(公告)号：US20230246002A1

公开(公告)日：2023-08-03

申请号：US18059646

申请日：2022-11-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Hiroshi YANAGIGAWA ,  Kazuhisa MORI ,  Toshiyuki HATA

IPC: H01L25/07 ,  H01L23/00 ,  H01L29/78

CPC classification number: H01L25/074 ,  H01L24/32 ,  H01L24/40 ,  H01L24/73 ,  H01L29/7805 ,  H01L29/7813 ,  H01L2224/32145 ,  H01L2224/40227 ,  H01L2224/73263 ,  H01L2924/13091 ,  H02M7/537

Abstract: A semiconductor device includes: a first semiconductor chip including a first MOSFET of n-type and a first parasitic diode; and a second semiconductor chip including a second MOSFET of n-type and a second parasitic diode. A first source electrode and a first gate wiring are formed in a first front surface of the first semiconductor chip, and a first drain electrode is formed in a first back surface of the first semiconductor chip. A second source electrode and a second gate wiring are formed in a second front surface of the second semiconductor chip, and a second drain electrode is formed in a second back surface of the second semiconductor chip. The first front surface and the second front surface face each other such that the first source electrode and the second source electrode are in contact with each other via a conductive paste.

公开(公告)号：US20210217844A1

公开(公告)日：2021-07-15

申请号：US17115204

申请日：2020-12-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi YANAGIGAWA ,  Katsumi EIKYU ,  Masami SAWADA ,  Akihiro SHIMOMURA ,  Kazuhisa MORI

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: In a trench gate type power MOSFET having a super-junction structure, both improvement of a breakdown voltage of a device and reduction of on-resistance are achieved. The trench gate and a column region are arranged so as to be substantially orthogonal to each other in a plan view, and a base region (channel forming region) and the column region are arranged separately in a cross-sectional view.