CPU/GPU DCVS CO-OPTIMIZATION FOR REDUCING POWER CONSUMPTION IN GRAPHICS FRAME PROCESSING
    1.
    发明申请
    CPU/GPU DCVS CO-OPTIMIZATION FOR REDUCING POWER CONSUMPTION IN GRAPHICS FRAME PROCESSING 有权
    CPU / GPU DCVS CO-OPTIMIZATION,用于降低图形帧处理中的功耗

    公开(公告)号:US20150317762A1

    公开(公告)日:2015-11-05

    申请号:US14266685

    申请日:2014-04-30

    Abstract: Systems, methods, and computer programs are disclosed for minimizing power consumption in graphics frame processing. One such method comprises: initiating graphics frame processing to be cooperatively performed by a central processing unit (CPU) and a graphics processing unit (GPU); receiving CPU activity data and GPU activity data; determining a set of available dynamic clock and voltage/frequency scaling (DCVS) levels for the GPU and the CPU; and selecting from the set of available DCVS levels an optimal combination of a GPU DCVS level and a CPU DCVS level, based on the CPU and GPU activity data, which minimizes a combined power consumption of the CPU and the GPU during the graphics frame processing.

    Abstract translation: 公开了用于使图形帧处理中的功率消耗最小化的系统,方法和计算机程序。 一种这样的方法包括:启动由中央处理单元(CPU)和图形处理单元(GPU)协同执行的图形帧处理; 接收CPU活动数据和GPU活动数据; 确定用于GPU和CPU的一组可用动态时钟和电压/频率缩放(DCVS)电平; 以及基于CPU和GPU活动数据,从可用DCVS级别中选择GPU DCVS级别和CPU DCVS级别的最佳组合,其在图形帧处理期间最小化CPU和GPU的组合功耗。

    METHOD AND SYSTEM FOR OPTIMIZING A CORE VOLTAGE LEVEL AND ENHANCING FREQUENCY PERFORMANCE OF INDIVIDUAL SUBCOMPONENTS FOR REDUCING POWER CONSUMPTION WITHIN A PCD
    2.
    发明申请
    METHOD AND SYSTEM FOR OPTIMIZING A CORE VOLTAGE LEVEL AND ENHANCING FREQUENCY PERFORMANCE OF INDIVIDUAL SUBCOMPONENTS FOR REDUCING POWER CONSUMPTION WITHIN A PCD 有权
    用于优化核心电压水平的方法和系统,并提高用于减少PCD中消耗电力的个人潜能的频率性能

    公开(公告)号:US20150143143A1

    公开(公告)日:2015-05-21

    申请号:US14187270

    申请日:2014-02-22

    CPC classification number: G06F1/3296 G06F1/26 G06F1/324 Y02D10/172

    Abstract: A method and system for optimizing a core voltage level of a portable computing device (“PCD”) and enhancing frequency performance of individual subcomponents are disclosed. A plurality of voltage values is determined for a plurality of subcomponents within the PCD. Next, a reduced set of voltage values may be calculated with a voltage aggregator based on the plurality of voltage values. An optimized voltage level for a shared power domain may then be determined by a voltage optimizer within the PCD from the reduced set of voltage values. A shared power domain may then be set to the optimized voltage level. Subsequently, an operating frequency of each subcomponent may be optimized with a frequency performance enhancer based on the optimized voltage level. An optimal power collapse duration may also be calculated by the frequency performance enhancer and set for each subcomponent from the optimal frequency.

    Abstract translation: 公开了一种用于优化便携式计算设备(“PCD”)的核心电压电平并提高各个子部件的频率性能的方法和系统。 为PCD内的多个子部件确定多个电压值。 接下来,可以使用电压聚合器基于多个电压值来计算减小的电压值集合。 然后,可以由PCD中的电压优化器从减小的电压值集合确定共享功率域的优化电压电平。 然后可以将共享电源域设置为优化的电压电平。 随后,可以使用基于优化的电压电平的频率性能增强器来优化每个子部件的工作频率。 也可以通过频率性能增强器来计算最佳功率衰减持续时间,并从最佳频率为每个子组件设置。

    SYSTEMS AND METHODS FOR DYNAMICALLY ADJUSTING MEMORY STATE TRANSITION TIMERS
    3.
    发明申请
    SYSTEMS AND METHODS FOR DYNAMICALLY ADJUSTING MEMORY STATE TRANSITION TIMERS 有权
    用于动态调整记忆状态转换定时器的系统和方法

    公开(公告)号:US20170068308A1

    公开(公告)日:2017-03-09

    申请号:US14846306

    申请日:2015-09-04

    Abstract: Systems, methods, and computer programs are disclosed for dynamically adjusting memory power state transition timers. One embodiment of a method comprises receiving one or more parameters impacting usage or performance of a memory device coupled to a processor in a computing device. An optimal value is determined for one or more memory power state transition timer settings. A current value is updated for the memory power state transition timer settings with the optimal value.

    Abstract translation: 公开了用于动态调整存储器功率状态转换定时器的系统,方法和计算机程序。 方法的一个实施例包括接收影响与计算设备中的处理器耦合的存储器件的使用或性能的一个或多个参数。 确定一个或多个存储器功率状态转换定时器设置的最佳值。 对于具有最佳值的存储器电源状态转换定时器设置,更新当前值。

    PEAK CURRENT SUPPORT FOR A POWER RAIL SYSTEM VIA A SHARED SECONDARY POWER SUPPLY

    公开(公告)号:US20170277238A1

    公开(公告)日:2017-09-28

    申请号:US15077949

    申请日:2016-03-23

    CPC classification number: G06F1/266 G06F1/263

    Abstract: Systems, methods, and computer programs are provided for controlling power in a computing device. One embodiment is a system comprising a plurality of power rails coupled to one or more computing device components. Each power rail has a primary power supply for producing current at a corresponding requested voltage. The system further comprises a shared secondary power supply selectively coupled to the plurality of power rails for providing a current increase. A controller selects one of the plurality of power rails to receive the current increase. The controller generates a control signal to electrically couple the shared secondary power supply to the selected power rail to receive the current increase.

    SYSTEMS AND METHODS FOR REDUCING LEAKAGE POWER OF A SYSTEM ON CHIP WITH INTEGRATED THERMOELECTRIC COOLING
    6.
    发明申请
    SYSTEMS AND METHODS FOR REDUCING LEAKAGE POWER OF A SYSTEM ON CHIP WITH INTEGRATED THERMOELECTRIC COOLING 审中-公开
    用于集成热电冷却的芯片系统的降低功率的系统和方法

    公开(公告)号:US20160033975A1

    公开(公告)日:2016-02-04

    申请号:US14446258

    申请日:2014-07-29

    Abstract: Systems, methods, and computer programs are disclosed for reducing leakage power of a system on chip (SoC). One such method comprises monitoring a plurality of temperature differentials across a respective plurality of thermoelectric coolers on a system on chip (SoC). Each of the thermoelectric coolers is dedicated to a corresponding one of a plurality of chip sections on the SoC. The thermoelectric coolers are controlled based on the plurality of temperature differentials to minimize a sum of a combined power consumption of the plurality of chip sections and the plurality of corresponding dedicated thermoelectric coolers.

    Abstract translation: 公开了用于降低片上系统(SoC)的泄漏功率的系统,方法和计算机程序。 一种这样的方法包括监视片上系统(SoC)上的相应多个热电冷却器上的多个温差。 每个热电冷却器专用于SoC上的多个芯片部分中的相应的一个。 基于多个温差来控制热电冷却器,以将多个芯片部分和多个相应的专用热电冷却器的组合功耗的总和最小化。

    Apparatus, System and Method for Dynamic Power Management Across Heterogeneous Processors in a Shared Power Domain
    7.
    发明申请
    Apparatus, System and Method for Dynamic Power Management Across Heterogeneous Processors in a Shared Power Domain 有权
    用于共享电源域中异构处理器的动态电源管理的装置,系统和方法

    公开(公告)号:US20150277536A1

    公开(公告)日:2015-10-01

    申请号:US14266642

    申请日:2014-04-30

    Abstract: Systems and methods for dynamically adjusting an input parameter to a power domain in a portable computing device are disclosed. The power domain includes two or more processing resources that share a power source. Dynamic use of the two or more processing resources creates an opportunity to adjust the input parameter when a status change associated with a processing resource in the power domain occurs. A controller in the power domain includes logic that responds to a status indicator associated with a respective processing resource in the power domain by generating a control signal that directs a device to adjust one or both of input voltage and clock frequency.

    Abstract translation: 公开了用于在便携式计算设备中动态调整输入参数到电力域的系统和方法。 功率域包括共享电源的两个或更多个处理资源。 当与功率域中的处理资源相关联的状态变化发生时,两个或多个处理资源的动态使用产生调整输入参数的机会。 功率域中的控制器包括通过产生引导设备调整输入电压和时钟频率中的一个或两者的控制信号来响应与功率域中的相应处理资源相关联的状态指示符的逻辑。

    METHOD AND SYSTEM FOR OPTIMIZING A CORE VOLTAGE LEVEL AND ENHANCING FREQUENCY PERFORMANCE OF INDIVIDUAL SUBCOMPONENTS FOR REDUCING POWER CONSUMPTION WITHIN A PCD
    8.
    发明申请
    METHOD AND SYSTEM FOR OPTIMIZING A CORE VOLTAGE LEVEL AND ENHANCING FREQUENCY PERFORMANCE OF INDIVIDUAL SUBCOMPONENTS FOR REDUCING POWER CONSUMPTION WITHIN A PCD 有权
    用于优化核心电压水平的方法和系统,并提高用于减少PCD中消耗电力的个人潜能的频率性能

    公开(公告)号:US20150143148A1

    公开(公告)日:2015-05-21

    申请号:US14338342

    申请日:2014-07-22

    CPC classification number: G06F1/3296 G06F1/26 G06F1/324 Y02D10/172

    Abstract: A method and system for optimizing a core voltage level of a portable computing device (“PCD”) and enhancing frequency performance of individual subcomponents are disclosed. A plurality of voltage values for a plurality of subsystems is determined. At least one subsystem is a multiplexed subsystem. Next, a reduced set of voltage values is calculated based on the plurality of voltage values and an optimized voltage level is determined for a shared power domain. The shared power domain is subsequently set to the optimized voltage level. If the optimized voltage level is determined to exceed a required voltage level for the at least one multiplexed subsystem when it is running the plurality of processing engines, a subset of the plurality of processing engines may be identified to process a workload of the multiplexed system at a more efficient level of power consumption than the full plurality of processing engines.

    Abstract translation: 公开了一种用于优化便携式计算设备(“PCD”)的核心电压电平并提高各个子部件的频率性能的方法和系统。 确定多个子系统的多个电压值。 至少一个子系统是多路复用子系统。 接下来,基于多个电压值计算减小的电压值集合,并且为共享电力域确定优化的电压电平。 共享电源域随后设置为优化的电压电平。 如果在运行多个处理引擎时,优选的电压电平被确定为超过所述至少一个多路复用子系统所需的电压电平,则可以识别多个处理引擎的子集以处理复用系统的工作负载 比全部多个处理引擎更有效的功耗水平。

    RUN-TIME NEURAL NETWORK RE-ALLOCATION ACROSS HETEROGENEOUS PROCESSORS

    公开(公告)号:US20210012207A1

    公开(公告)日:2021-01-14

    申请号:US16506913

    申请日:2019-07-09

    Abstract: Neural network workload re-allocation in a system-on-chip having multiple heterogenous processors executing one or more neural network units may be based on measurements associated with the processors' conditions and on metadata associated with the neural network units. Metadata may be contained in an input file along with neural network information. Measurements characterizing operation of the processors may be obtained and compared with one or more thresholds. A neural network unit executing on a processor may be identified as a candidate for re-allocation based on metadata associated with the neural network unit and results of the comparisons. A target processor may be identified based on the metadata and results of the comparisons, and the candidate neural network neural network unit may be re-allocated to the target processor.

    SYSTEM AND METHOD FOR MODEM MANAGEMENT BASED ON KEY PERFORMANCE INDICATORS

    公开(公告)号:US20170099204A1

    公开(公告)日:2017-04-06

    申请号:US14873154

    申请日:2015-10-01

    Abstract: Various embodiments of methods and systems for modem management in a portable computing device are disclosed. An exemplary method recognizes an input of a key performance indicator (“KPI”) from a plurality of performance indicators. Based on the key performance indicator either manually by a user or automatically based on system status information, the exemplary method determines a particular modem management and control strategy designed to optimize performance of the modem based on the key performance indicator. The determined modem management and control strategy is implemented to cause adjustment of a modem performance level such that the key performance indicator is optimized. Exemplary KPIs include, lower device temperature, maximization of the percentage of time that the modem is operating at a maximum advertised LTE speed, maximization of the average data throughput, maximization of battery life, and minimizing LTE speed transitions over time.

Patent Agency Ranking