公开(公告)号：US20150286262A1

公开(公告)日：2015-10-08

申请号：US14280629

申请日：2014-05-18

Applicant: QUALCOMM INCORPORATED

Inventor： HEE JUN PARK ,  YOUNG HOON KANG ,  RONALD FRANK ALTON ,  CHRISTOPER LEE MEDRANO ,  JON JAMES ANDERSON

IPC: G06F1/32

CPC classification number: G05D23/1917 ,  G05B15/02 ,  G06F1/203 ,  G06F1/206 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/30 ,  G06F11/34 ,  Y02D10/16

Abstract: Various embodiments of methods and systems for energy efficiency aware thermal management in a portable computing device that contains a heterogeneous, multi-processor system on a chip (“SoC”) are disclosed. Because individual processing components in a heterogeneous, multi-processor SoC may exhibit different processing efficiencies at a given temperature, energy efficiency aware thermal management techniques that compare performance data of the individual processing components at their measured operating temperatures can be leveraged to optimize quality of service (“QoS”) by adjusting the power supplies to, reallocating workloads away from, or transitioning the power mode of, the least energy efficient processing components. In these ways, embodiments of the solution optimize the average amount of power consumed across the SoC to process a MIPS of workload.

Abstract translation: 公开了在包含芯片上的异构多处理器系统（“SoC”）的便携式计算设备中的用于能量效率感知热管理的方法和系统的各种实施例。 由于异构多处理器SoC中的单独处理组件可能在给定温度下可能表现出不同的处理效率，因此可以利用能源效率感知热管理技术来比较其测量工作温度下各个处理组件的性能数据，从而优化服务质量 （“QoS”），通过调整电力供应，重新分配工作量远离或转移最低能效处理组件的功率模式。 以这些方式，该解决方案的实施例优化了跨SoC消耗的平均功耗量以处理MIPS的工作负载。

公开(公告)号：US20150286257A1

公开(公告)日：2015-10-08

申请号：US14280631

申请日：2014-05-18

Applicant: QUALCOMM INCORPORATED

Inventor： HEE JUN PARK ,  YOUNG HOON KANG ,  RONALD FRANK ALTON ,  CHRISTOPHER LEE MEDRANO ,  JON JAMES ANDERSON

IPC: G06F1/20

CPC classification number: G05D23/1917 ,  G05B15/02 ,  G06F1/203 ,  G06F1/206 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/30 ,  G06F11/34 ,  Y02D10/16

Abstract: Various embodiments of methods and systems for energy efficiency aware thermal management in a portable computing device that contains a heterogeneous, multi-processor system on a chip (“SoC”) are disclosed. Because individual processing components in a heterogeneous, multi-processor SoC may exhibit different processing efficiencies at a given temperature, energy efficiency aware thermal management techniques that compare performance data of the individual processing components at their measured operating temperatures can be leveraged to optimize quality of service (“QoS”) by adjusting the power supplies to, reallocating workloads away from, or transitioning the power mode of, the least energy efficient processing components. In these ways, embodiments of the solution optimize the average amount of power consumed across the SoC to process a MIPS of workload.

公开(公告)号：US20150286225A1

公开(公告)日：2015-10-08

申请号：US14280630

申请日：2014-05-18

Applicant: QUALCOMM INCORPORATED

Inventor： HEE JUN PARK ,  YOUNG HOON KANG ,  RONALD FRANK ALTON ,  CHRISTOPHER LEE MEDRANO ,  JON JAMES ANDERSON

IPC: G05D23/19 ,  G05B15/02

CPC classification number: G05D23/1917 ,  G05B15/02 ,  G06F1/203 ,  G06F1/206 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/30 ,  G06F11/34 ,  Y02D10/16

Abstract: Various embodiments of methods and systems for energy efficiency aware thermal management in a portable computing device that contains a heterogeneous, multi-processor system on a chip (“SoC”) are disclosed. Because individual processing components in a heterogeneous, multi-processor SoC may exhibit different processing efficiencies at a given temperature, energy efficiency aware thermal management techniques that compare performance data of the individual processing components at their measured operating temperatures can be leveraged to optimize quality of service (“QoS”) by adjusting the power supplies to, reallocating workloads away from, or transitioning the power mode of, the least energy efficient processing components. In these ways, embodiments of the solution optimize the average amount of power consumed across the SoC to process a MIPS of workload.

公开(公告)号：US20160033975A1

公开(公告)日：2016-02-04

申请号：US14446258

申请日：2014-07-29

Applicant: QUALCOMM INCORPORATED

Inventor： RAJAT MITTAL ,  HEE JUN PARK ,  YOUNG HOON KANG

IPC: G05D23/19 ,  G05B13/02

CPC classification number: G05D23/1917 ,  G05B13/0205 ,  G06F1/206 ,  G06F1/3206 ,  H01L23/34 ,  H01L23/38 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/072 ,  H01L2924/0002 ,  Y02D10/16 ,  H01L2924/00

Abstract: Systems, methods, and computer programs are disclosed for reducing leakage power of a system on chip (SoC). One such method comprises monitoring a plurality of temperature differentials across a respective plurality of thermoelectric coolers on a system on chip (SoC). Each of the thermoelectric coolers is dedicated to a corresponding one of a plurality of chip sections on the SoC. The thermoelectric coolers are controlled based on the plurality of temperature differentials to minimize a sum of a combined power consumption of the plurality of chip sections and the plurality of corresponding dedicated thermoelectric coolers.

Abstract translation: 公开了用于降低片上系统（SoC）的泄漏功率的系统，方法和计算机程序。 一种这样的方法包括监视片上系统（SoC）上的相应多个热电冷却器上的多个温差。 每个热电冷却器专用于SoC上的多个芯片部分中的相应的一个。 基于多个温差来控制热电冷却器，以将多个芯片部分和多个相应的专用热电冷却器的组合功耗的总和最小化。

公开(公告)号：US20150143148A1

公开(公告)日：2015-05-21

申请号：US14338342

申请日：2014-07-22

Applicant: QUALCOMM INCORPORATED

Inventor： HEE JUN PARK ,  YIRAN LEE ,  INHO HWANG ,  YOUNG HOON KANG ,  JOSHUA HIRSCH STUBBS ,  SEAN SWEENEY ,  ROBERT NICHOLSON GIBSON ,  ANDREW JAMES FRANTZ ,  VISWANATHAN KUMARAGURUBARAN ,  SUMANT MADHAV PARANJPE

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/324 ,  Y02D10/172

Abstract: A method and system for optimizing a core voltage level of a portable computing device (“PCD”) and enhancing frequency performance of individual subcomponents are disclosed. A plurality of voltage values for a plurality of subsystems is determined. At least one subsystem is a multiplexed subsystem. Next, a reduced set of voltage values is calculated based on the plurality of voltage values and an optimized voltage level is determined for a shared power domain. The shared power domain is subsequently set to the optimized voltage level. If the optimized voltage level is determined to exceed a required voltage level for the at least one multiplexed subsystem when it is running the plurality of processing engines, a subset of the plurality of processing engines may be identified to process a workload of the multiplexed system at a more efficient level of power consumption than the full plurality of processing engines.

Abstract translation: 公开了一种用于优化便携式计算设备（“PCD”）的核心电压电平并提高各个子部件的频率性能的方法和系统。 确定多个子系统的多个电压值。 至少一个子系统是多路复用子系统。 接下来，基于多个电压值计算减小的电压值集合，并且为共享电力域确定优化的电压电平。 共享电源域随后设置为优化的电压电平。 如果在运行多个处理引擎时，优选的电压电平被确定为超过所述至少一个多路复用子系统所需的电压电平，则可以识别多个处理引擎的子集以处理复用系统的工作负载 比全部多个处理引擎更有效的功耗水平。

公开(公告)号：US20150317762A1

公开(公告)日：2015-11-05

申请号：US14266685

申请日：2014-04-30

Applicant: Qualcomm Incorporated

Inventor： HEE JUN PARK ,  YOUNG HOON KANG ,  MRIGANKA MONDAL

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  G09G2330/021 ,  G09G2360/06 ,  Y02D10/126 ,  Y02D10/172

Abstract: Systems, methods, and computer programs are disclosed for minimizing power consumption in graphics frame processing. One such method comprises: initiating graphics frame processing to be cooperatively performed by a central processing unit (CPU) and a graphics processing unit (GPU); receiving CPU activity data and GPU activity data; determining a set of available dynamic clock and voltage/frequency scaling (DCVS) levels for the GPU and the CPU; and selecting from the set of available DCVS levels an optimal combination of a GPU DCVS level and a CPU DCVS level, based on the CPU and GPU activity data, which minimizes a combined power consumption of the CPU and the GPU during the graphics frame processing.

Abstract translation: 公开了用于使图形帧处理中的功率消耗最小化的系统，方法和计算机程序。 一种这样的方法包括：启动由中央处理单元（CPU）和图形处理单元（GPU）协同执行的图形帧处理; 接收CPU活动数据和GPU活动数据; 确定用于GPU和CPU的一组可用动态时钟和电压/频率缩放（DCVS）电平; 以及基于CPU和GPU活动数据，从可用DCVS级别中选择GPU DCVS级别和CPU DCVS级别的最佳组合，其在图形帧处理期间最小化CPU和GPU的组合功耗。

公开(公告)号：US20150143143A1

公开(公告)日：2015-05-21

申请号：US14187270

申请日：2014-02-22

Applicant: QUALCOMM INCORPORATED

Inventor： HEE JUN PARK ,  YIRAN LI ,  INHO HWANG ,  YOUNG HOON KANG ,  JOSHUA STUBBS ,  SEAN SWEENEY ,  R. NICHOLSON GIBSON ,  ANDREW J. FRANTZ

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/324 ,  Y02D10/172

Abstract: A method and system for optimizing a core voltage level of a portable computing device (“PCD”) and enhancing frequency performance of individual subcomponents are disclosed. A plurality of voltage values is determined for a plurality of subcomponents within the PCD. Next, a reduced set of voltage values may be calculated with a voltage aggregator based on the plurality of voltage values. An optimized voltage level for a shared power domain may then be determined by a voltage optimizer within the PCD from the reduced set of voltage values. A shared power domain may then be set to the optimized voltage level. Subsequently, an operating frequency of each subcomponent may be optimized with a frequency performance enhancer based on the optimized voltage level. An optimal power collapse duration may also be calculated by the frequency performance enhancer and set for each subcomponent from the optimal frequency.

Abstract translation: 公开了一种用于优化便携式计算设备（“PCD”）的核心电压电平并提高各个子部件的频率性能的方法和系统。 为PCD内的多个子部件确定多个电压值。 接下来，可以使用电压聚合器基于多个电压值来计算减小的电压值集合。 然后，可以由PCD中的电压优化器从减小的电压值集合确定共享功率域的优化电压电平。 然后可以将共享电源域设置为优化的电压电平。 随后，可以使用基于优化的电压电平的频率性能增强器来优化每个子部件的工作频率。 也可以通过频率性能增强器来计算最佳功率衰减持续时间，并从最佳频率为每个子组件设置。