公开(公告)号：US09384795B1

公开(公告)日：2016-07-05

申请号：US14698843

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： David Paul Hoff ,  Jason Philip Martzloff ,  Robert Andrew Sweitzer

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/22

CPC classification number: G11C7/106 ,  G11C7/10 ,  G11C7/1009 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C11/419

Abstract: In an array that qualifies each row according to a valid/invalid state, each row may each include valid-gated read circuitry to conditionally block a read wordline from toggling unless the row stores a data word that has a valid state or a read force signal is asserted. Furthermore, in a write operation, each row may have valid-gated write circuitry that conditionally blocks a write wordline from toggling unless input data to be written to the row has a valid state or a write force signal is asserted. Moreover, output latch clocking may be blocked from toggling unless a row to be read stores a data word that has a valid state or the read force signal is asserted, and input latch clocking may also be blocked unless the input data to be written has a valid state or the write force signal is asserted.

Abstract translation: 在根据有效/无效状态对每行进行限定的数组中，每行可以包括有效门控读取电路，以有条件地阻止读取字线切换，除非该行存储具有有效状态或读取强制信号的数据字 被断言。 此外，在写入操作中，每行可以具有有效门控写入电路，其有条件地阻止写入字线切换，除非要写入行的输入数据具有有效状态或写入强制信号被断言。 此外，除非要读取的行存储具有有效状态的数据字或读取强制信号被断言，否则输出锁存时钟可能被阻止，并且输入锁存时钟也可能被阻塞，除非要写入的输入数据具有 有效状态或写力信号被断言。

公开(公告)号：US09003111B2

公开(公告)日：2015-04-07

申请号：US13969636

申请日：2013-08-19

Applicant: QUALCOMM Incorporated

Inventor： Manju Rathna Varma ,  David Paul Hoff ,  Jason Philip Martzloff

IPC: G06F12/00 ,  G11C15/00 ,  G11C15/04

CPC classification number: G06F12/00 ,  G11C15/04

Abstract: Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell configured to generate a match indicator, and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell is blocked from affecting the match indicator for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation.

Abstract translation: 公开了能够进行高速搜索和无效操作的内容可寻址存储器（CAM）的实施例及其操作方法。 在一个实施例中，CAM包括包括多个CAM单元的CAM单元阵列和被配置为产生匹配指示符的有效位单元，以及阻塞电路，配置为阻止有效位单元的输出在无效期间改变匹配指示符 搜索过程和无效操作。 优选地，阻止有效位单元的输出影响在无效过程开始时开始的CAM单元阵列的匹配指示符，并且继续直到搜索结束和无效操作。

公开(公告)号：US20170053685A1

公开(公告)日：2017-02-23

申请号：US15087219

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Milind Ram Kulkarni ,  David Paul Hoff

IPC: G11C8/10 ,  G11C8/18

CPC classification number: G11C8/10 ,  G11C8/12 ,  G11C8/18

Abstract: Multiple-hot (multi-hot) bit decoding in a memory system for activating multiple memory locations in a memory for a memory access operation are disclosed. In one aspect, a multi-hot bit decoding system is provided that includes a memory access control system that includes a decoder. The decoder is configured to decode an address for a memory access operation into a single-hot bit decode word for activating a memory row at the encoded address. To automatically access another memory row(s) for a memory access operation, the memory access control system also includes a mapping circuit configured to provide an additional decode word(s) for activating another memory row(s) based on the address. The decode word and additional decode word(s) are merged to provide a multi-hot bit decode word that is asserted onto a decode wordline such that multiple memory rows are activated for a memory access operation.

Abstract translation: 公开了一种用于激活用于存储器访问操作的存储器中的多个存储器位置的存储器系统中的多热（多热）位解码。 一方面，提供一种多热位解码系统，其包括包括解码器的存储器访问控制系统。 解码器被配置为将用于存储器访问操作的地址解码为用于激活编码地址处的存储器行的单个热位解码字。 为了自动访问用于存储器访问操作的另一存储器行，存储器访问控制系统还包括映射电路，其被配置为基于该地址提供用于激活另一个存储器行的附加解码字。 合并解码字和附加解码字以提供被断言在解码字线上的多位热解码字，使得多个存储器行被激活用于存储器访问操作。

公开(公告)号：US09378789B2

公开(公告)日：2016-06-28

申请号：US14499035

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： David Paul Hoff ,  Amey Kulkarni ,  Jason Philip Martzloff ,  Stephen Edward Liles

IPC: G11C7/12 ,  H03K3/356

CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/1096 ,  G11C11/419 ,  H03K3/356104 ,  H03K3/35613 ,  H03K3/356139 ,  H03K3/356165 ,  H03K3/356173

Abstract: Systems and methods for generating voltage level shifted self-clocked write assistance include a circuit with self-clocked true and complement data input signals in a first voltage domain. First and second full voltage level shifters are configured to generate voltage level shifted self-clocked intermediate true and complement signals in a second voltage domain, based on the self-clocked true and complement data input signals in the first voltage domain. Tristating logic including first and second complementary metal oxide semiconductor (CMOS) circuits are configured to generate voltage level shifted self-clocked tristated true and complement output signals used for providing write assistance for a memory array in the second voltage domain, based on the voltage level shifted self-clocked intermediate true and complements signals.

Abstract translation: 用于产生电压电平转换的自适应写入辅助的系统和方法包括在第一电压域中具有自定时真实和补码数据输入信号的电路。 第一和第二全电压电平移位器被配置为基于第一电压域中的自计时真实和补码数据输入信号，在第二电压域中产生电压电平移位的自适应中间真和互补信号。 包括第一和第二互补金属氧化物半导体（CMOS）电路的三态逻辑被配置为基于电压电平产生用于向第二电压域中的存储器阵列提供写入辅助的电压电平移位的自定时三态真和补输出信号 改变自我中频真实和补充信号。

公开(公告)号：US09165650B2

公开(公告)日：2015-10-20

申请号：US13798767

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： David Paul Hoff ,  Tracey A. Della Rova ,  Jason P. Martzloff

IPC: G11C15/04 ,  G06F7/74

CPC classification number: G11C15/04 ,  G06F7/74 ,  G11C15/043 ,  H03K19/0013

Abstract: The hybrid dynamic-static encoder described herein may combine dynamic and static structural and logical design features that strategically partition dynamic nets and logic to substantially eliminate redundancy and thereby provide area, power, and leakage savings relative to a fully dynamic encoder with an equivalent logic delay. For example, the hybrid dynamic-static encoder may include identical top and bottom halves, which may be combined to produce final encoded index, hit, and multi-hit outputs. Each encoder half may use a dynamic net for each index bit with rows that match a search key dotted. If a row has been dotted to indicate that the row matches the search key, the dynamic nets associated therewith may be evaluated to reflect the index associated with the row. Accordingly, the hybrid dynamic-static encoder may have a reduced set of smaller dynamic nets that leverage redundant pull-down structures across the index, hit, and multi-hit dynamic nets.

Abstract translation: 本文描述的混合动态静态编码器可以组合动态和静态结构和逻辑设计特征，其策略性地分割动态网络和逻辑以基本上消除冗余，从而相对于具有等效逻辑延迟的全动态编码器提供面积，功率和泄漏节省 。 例如，混合动态静态编码器可以包括相同的顶部和底部两半，其可以被组合以产生最终编码索引，命中和多命中输出。 每个编码器一半可以为每个索引位使用动态网络，其中匹配搜索关键点的行。 如果已经点划线以指示该行与搜索关键字匹配，则可以评估与之相关联的动态网络以反映与该行相关联的索引。 因此，混合动态静态编码器可以具有减小的较小动态网络集合，其利用索引，命中和多命中动态网络上的冗余下拉结构。

公开(公告)号：US20140119102A1

公开(公告)日：2014-05-01

申请号：US13787875

申请日：2013-03-07

Applicant: QUALCOMM INCORPORATED

Inventor： Harish Shankar ,  David Paul Hoff ,  Manish Garg

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C5/063 ,  G11C8/08 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

Abstract: Systems and methods for detecting and suppressing crowbar currents in memory arrays. A dummy read is implemented to prevent crowbar currents in the case of simultaneous read-write collisions in a static random access memory (SRAM) array having cross-coupled bitline keepers. When a simultaneous read and write operation to a first entry of the memory array is detected, the read operation to the first entry is suppressed and a dummy read operation to a second entry of the memory array is performed. The write operation to the first entry is allowed to proceed undisturbed.

Abstract translation: 用于检测和抑制存储器阵列中的电涌电流的系统和方法。 在具有交叉耦合的位线保持器的静态随机存取存储器（SRAM）阵列中，实现了虚拟读取以防止在同时读写冲突的情况下的撬棒电流。 当检测到对存储器阵列的第一条目的同时读取和写入操作时，对第一条目的读取操作被抑制，并且执行对存储器阵列的第二条目的伪读取操作。 允许对第一个条目的写入操作不受干扰。

公开(公告)号：US09830965B2

公开(公告)日：2017-11-28

申请号：US15087219

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Milind Ram Kulkarni ,  David Paul Hoff

IPC: G11C8/10 ,  G11C8/18

CPC classification number: G11C8/10 ,  G11C8/12 ,  G11C8/18

Abstract: Multiple-hot (multi-hot) bit decoding in a memory system for activating multiple memory locations in a memory for a memory access operation are disclosed. In one aspect, a multi-hot bit decoding system is provided that includes a memory access control system that includes a decoder. The decoder is configured to decode an address for a memory access operation into a single-hot bit decode word for activating a memory row at the encoded address. To automatically access another memory row(s) for a memory access operation, the memory access control system also includes a mapping circuit configured to provide an additional decode word(s) for activating another memory row(s) based on the address. The decode word and additional decode word(s) are merged to provide a multi-hot bit decode word that is asserted onto a decode wordline such that multiple memory rows are activated for a memory access operation.

公开(公告)号：US09129706B2

公开(公告)日：2015-09-08

申请号：US13787875

申请日：2013-03-07

Applicant: QUALCOMM Incorporated

Inventor： Harish Shankar ,  David Paul Hoff ,  Manish Garg

IPC: G11C11/412 ,  G11C5/06 ,  G11C8/16 ,  G11C8/00 ,  G11C8/08 ,  G11C11/413 ,  G11C11/418

CPC classification number: G11C11/412 ,  G11C5/063 ,  G11C8/08 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

Abstract: Systems and methods for detecting and suppressing crowbar currents in memory arrays. A dummy read is implemented to prevent crowbar currents in the case of simultaneous read-write collisions in a static random access memory (SRAM) array having cross-coupled bitline keepers. When a simultaneous read and write operation to a first entry of the memory array is detected, the read operation to the first entry is suppressed and a dummy read operation to a second entry of the memory array is performed. The write operation to the first entry is allowed to proceed undisturbed.

Abstract translation: 用于检测和抑制存储器阵列中的电涌电流的系统和方法。 在具有交叉耦合的位线保持器的静态随机存取存储器（SRAM）阵列中，实现了虚拟读取以防止在同时读写冲突的情况下的撬棒电流。 当检测到对存储器阵列的第一条目的同时读取和写入操作时，对第一条目的读取操作被抑制，并且执行对存储器阵列的第二条目的伪读取操作。 允许对第一个条目的写入操作不受干扰。

公开(公告)号：US20130339597A1

公开(公告)日：2013-12-19

申请号：US13969636

申请日：2013-08-19

Applicant: QUALCOMM Incorporated

Inventor： Manju Rathna Varma ,  David Paul Hoff ,  Jason Philip Martzloff

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G11C15/04

Abstract: Embodiments of a Content Addressable Memory (CAM) enabling high-speed search and invalidate operations and methods of operation thereof are disclosed. In one embodiment, the CAM includes a CAM cell array including a number of CAM cells and a valid bit cell configured to generate a match indicator, and blocking circuitry configured to block an output of the valid bit cell from altering the match indicator during an invalidate process of a search and invalidate operation. Preferably, the output of the valid bit cell is blocked from affecting the match indicator for the CAM cell array beginning at a start of the invalidate process and continuing until an end of the search and invalidate operation.

Abstract translation: 公开了能够进行高速搜索和无效操作的内容可寻址存储器（CAM）的实施例及其操作方法。 在一个实施例中，CAM包括包括多个CAM单元的CAM单元阵列和被配置为产生匹配指示符的有效位单元，以及阻塞电路，配置为阻止有效位单元的输出在无效期间改变匹配指示符 搜索过程和无效操作。 优选地，阻止有效位单元的输出影响在无效过程开始时开始的CAM单元阵列的匹配指示符，并且继续直到搜索结束和无效操作。

公开(公告)号：US09852080B2

公开(公告)日：2017-12-26

申请号：US15087077

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： David Paul Hoff ,  Milind Ram Kulkarni ,  Benjamin John Bowers

IPC: G06F12/10 ,  G06F12/0879 ,  G06F12/0895 ,  G06F1/06 ,  G06F12/14 ,  G06F12/1027

CPC classification number: G06F12/10 ,  G06F1/06 ,  G06F12/0879 ,  G06F12/0895 ,  G06F12/1027 ,  G06F12/1441 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/65

Abstract: Efficiently generating selection masks for row selections within indexed address spaces is disclosed. In this regard, in one aspect, an indexed array circuit is provided, comprising a start indicator that indicates a start indexed array row of a row selection, and an end indicator that indicates an end indexed array row of the row selection. The indexed array circuit further comprises a plurality of indexed array rows ordered in a logical sequence, each comprising a row-level compare circuit. Each row-level compare circuit is configured to generate a selection mask indicator based on a first parallel comparison of subsets of bits of a logical address of the indexed array row with corresponding subsets of bits of the start indicator, and a second parallel comparison of subsets of bits of the logical address of the indexed array row with corresponding subsets of bits of the end indicator.