公开(公告)号：US09666269B2

公开(公告)日：2017-05-30

申请号：US14857512

申请日：2015-09-17

Applicant: QUALCOMM Incorporated

Inventor： Harish Shankar ,  Manish Garg ,  Joshua Lance Puckett ,  Rahul Krishnakumar Nadkarni

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/10 ,  G11C8/16

CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C8/16

Abstract: Collision detection systems for detecting read-write collisions in memory systems after word line activation are disclosed. In one aspect, a collision detection system is provided. The collision detection system includes a collision detection circuit for each bit cell row of memory array. Each collision detection circuit is configured to receive a write and read word line signal corresponding to the bit cell row. The collision detection circuit is configured to detect a write and read word line signal pair being active for a write and read operation for the same bit cell row. The collision detection circuit is configured to generate a collision detection signal to notify clients associated with the memory system that a read-write collision occurred. Detecting the read-write collisions after read word line activation reduces or avoids overhead delays in the read path, as opposed to detecting read-write collisions prior to activation of the read word line.

公开(公告)号：US10599566B2

公开(公告)日：2020-03-24

申请号：US15647202

申请日：2017-07-11

Applicant: QUALCOMM Incorporated

Inventor： Ramasamy Adaikkalavan ,  Harish Shankar ,  Rajesh Kumar

IPC: G06F12/0808 ,  G06F16/903 ,  G11C15/04 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1045

Abstract: Systems and methods for cache invalidation, with support for different modes of cache invalidation include receiving a matchline signal, wherein the matchline signal indicates whether there is a match between a search word and an entry of a tag array of the cache. The matchline signal is latched in a latch controlled by a function of a single bit mismatch clock, wherein a rising edge of the single bit mismatch clock is based on delay for determining a single bit mismatch between the search word and the entry of the tag array. An invalidate signal for invalidating a cacheline corresponding to the entry of the tag array is generated at an output of the latch. Circuit complexity is reduced by gating a search word with a search-invalidate signal, such that the gated search word corresponds to the search word for a search-invalidate and to zero for a Flash-invalidate.

公开(公告)号：US20160240244A1

公开(公告)日：2016-08-18

申请号：US14857512

申请日：2015-09-17

Applicant: QUALCOMM Incorporated

Inventor： Harish Shankar ,  Manish Garg ,  Joshua Lance Puckett ,  Rahul Krishnakumar Nadkarni

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C8/16

Abstract: Collision detection systems for detecting read-write collisions in memory systems after word line activation are disclosed. In one aspect, a collision detection system is provided. The collision detection system includes a collision detection circuit for each bit cell row of memory array. Each collision detection circuit is configured to receive a write and read word line signal corresponding to the bit cell row. The collision detection circuit is configured to detect a write and read word line signal pair being active for a write and read operation for the same bit cell row. The collision detection circuit is configured to generate a collision detection signal to notify clients associated with the memory system that a read-write collision occurred. Detecting the read-write collisions after read word line activation reduces or avoids overhead delays in the read path, as opposed to detecting read-write collisions prior to activation of the read word line.

Abstract translation: 公开了用于在字线激活之后检测存储器系统中的读写冲突的冲突检测系统。 一方面，提供了一种碰撞检测系统。 碰撞检测系统包括用于存储器阵列的每个比特单元行的冲突检测电路。 每个碰撞检测电路被配置为接收对应于位单元行的写入和读取字线信号。 冲突检测电路被配置为检测对同一位单元行的写入和读取操作有效的写入和读取字线信号对。 冲突检测电路被配置为产生冲突检测信号，以通知与存储器系统相关联的客户发生读写冲突。 在读取字线激活之后检测读写冲突减少或避免读取路径中的开销延迟，而不是在激活读取字线之前检测读写冲突。

公开(公告)号：US10559352B2

公开(公告)日：2020-02-11

申请号：US16134937

申请日：2018-09-18

Applicant: QUALCOMM Incorporated

Inventor： Harish Shankar ,  Manish Garg ,  Rahul Krishnakumar Nadkarni ,  Rajesh Kumar ,  Michael Phan

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/08 ,  G11C8/18 ,  G11C7/10 ,  G11C11/418

Abstract: A memory system includes a sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array, a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline, and a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output, and wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor.

公开(公告)号：US20140119102A1

公开(公告)日：2014-05-01

申请号：US13787875

申请日：2013-03-07

Applicant: QUALCOMM INCORPORATED

Inventor： Harish Shankar ,  David Paul Hoff ,  Manish Garg

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C5/063 ,  G11C8/08 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

Abstract: Systems and methods for detecting and suppressing crowbar currents in memory arrays. A dummy read is implemented to prevent crowbar currents in the case of simultaneous read-write collisions in a static random access memory (SRAM) array having cross-coupled bitline keepers. When a simultaneous read and write operation to a first entry of the memory array is detected, the read operation to the first entry is suppressed and a dummy read operation to a second entry of the memory array is performed. The write operation to the first entry is allowed to proceed undisturbed.

Abstract translation: 用于检测和抑制存储器阵列中的电涌电流的系统和方法。 在具有交叉耦合的位线保持器的静态随机存取存储器（SRAM）阵列中，实现了虚拟读取以防止在同时读写冲突的情况下的撬棒电流。 当检测到对存储器阵列的第一条目的同时读取和写入操作时，对第一条目的读取操作被抑制，并且执行对存储器阵列的第二条目的伪读取操作。 允许对第一个条目的写入操作不受干扰。

公开(公告)号：US09129706B2

公开(公告)日：2015-09-08

申请号：US13787875

申请日：2013-03-07

Applicant: QUALCOMM Incorporated

Inventor： Harish Shankar ,  David Paul Hoff ,  Manish Garg

IPC: G11C11/412 ,  G11C5/06 ,  G11C8/16 ,  G11C8/00 ,  G11C8/08 ,  G11C11/413 ,  G11C11/418

CPC classification number: G11C11/412 ,  G11C5/063 ,  G11C8/08 ,  G11C8/16 ,  G11C11/413 ,  G11C11/418

Abstract: Systems and methods for detecting and suppressing crowbar currents in memory arrays. A dummy read is implemented to prevent crowbar currents in the case of simultaneous read-write collisions in a static random access memory (SRAM) array having cross-coupled bitline keepers. When a simultaneous read and write operation to a first entry of the memory array is detected, the read operation to the first entry is suppressed and a dummy read operation to a second entry of the memory array is performed. The write operation to the first entry is allowed to proceed undisturbed.

Abstract translation: 用于检测和抑制存储器阵列中的电涌电流的系统和方法。 在具有交叉耦合的位线保持器的静态随机存取存储器（SRAM）阵列中，实现了虚拟读取以防止在同时读写冲突的情况下的撬棒电流。 当检测到对存储器阵列的第一条目的同时读取和写入操作时，对第一条目的读取操作被抑制，并且执行对存储器阵列的第二条目的伪读取操作。 允许对第一个条目的写入操作不受干扰。

公开(公告)号：US09093125B2

公开(公告)日：2015-07-28

申请号：US13746528

申请日：2013-01-22

Applicant: QUALCOMM Incorporated

Inventor： Joshua L. Puckett ,  Manish Garg ,  Harish Shankar

IPC: G11C7/00 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C7/00 ,  G11C11/412 ,  G11C11/419

Abstract: In low power CPUs, the best way to reduce power is to reduce supply voltage. Most low voltage memory arrays use an 8T cell, which has read stability immunity, in order to operate at low voltages. An embodiment of the disclosure determines when a write wordline (WWL) rises. If the determination shows that the WWL has risen, at least one of the plurality of p-channel field effect transistors (pFETS) is disconnected from a voltage supply, and the at least one plurality of n-channel field effect transistors (nFET) passgate transistors are opened.

Abstract translation: 在低功耗CPU中，降低功耗的最佳方法是降低电源电压。 大多数低电压存储器阵列使用具有读稳定性抗扰度的8T电池，以便在低电压下工作。 本公开的实施例确定写入字线（WWL）何时上升。 如果确定显示WWL已经升高，则多个p沟道场效应晶体管（pFETS）中的至少一个与电压源断开，并且至少一个多个n沟道场效应晶体管（nFET）通孔 晶体管被打开。

公开(公告)号：US20130188434A1

公开(公告)日：2013-07-25

申请号：US13746528

申请日：2013-01-22

Applicant: QUALCOMM INCORPORATED

Inventor： Joshua L. Puckett ,  Manish Garg ,  Harish Shankar

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C11/412 ,  G11C11/419

Abstract: In low power CPUs, the best way to reduce power is to reduce supply voltage. Most low voltage memory arrays use an 8T cell, which has read stability immunity, in order to operate at low voltages. An embodiment of the disclosure determines when a write wordline (WWL) rises. If the determination shows that the WWL has risen, at least one of the plurality of p-channel field effect transistors (pFETS) is disconnected from a voltage supply, and the at least one plurality of n-channel field effect transistors (nFET) passe ate transistors are opened.

Abstract translation: 在低功耗CPU中，降低功耗的最佳方法是降低电源电压。 大多数低电压存储器阵列使用具有读稳定性抗扰度的8T电池，以便在低电压下工作。 本公开的实施例确定写入字线（WWL）何时上升。 如果确定表明WWL已经升高，则多个p沟道场效应晶体管（pFETS）中的至少一个与电压源断开，并且至少一个多个n沟道场效应晶体管（nFET）passe 打开晶体管。