公开(公告)号：US10599566B2

公开(公告)日：2020-03-24

申请号：US15647202

申请日：2017-07-11

Applicant: QUALCOMM Incorporated

Inventor： Ramasamy Adaikkalavan ,  Harish Shankar ,  Rajesh Kumar

IPC: G06F12/0808 ,  G06F16/903 ,  G11C15/04 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1045

Abstract: Systems and methods for cache invalidation, with support for different modes of cache invalidation include receiving a matchline signal, wherein the matchline signal indicates whether there is a match between a search word and an entry of a tag array of the cache. The matchline signal is latched in a latch controlled by a function of a single bit mismatch clock, wherein a rising edge of the single bit mismatch clock is based on delay for determining a single bit mismatch between the search word and the entry of the tag array. An invalidate signal for invalidating a cacheline corresponding to the entry of the tag array is generated at an output of the latch. Circuit complexity is reduced by gating a search word with a search-invalidate signal, such that the gated search word corresponds to the search word for a search-invalidate and to zero for a Flash-invalidate.

公开(公告)号：US09960759B2

公开(公告)日：2018-05-01

申请号：US14860713

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Manish Garg ,  Ramasamy Adaikkalavan

IPC: G06F12/08 ,  G06F7/02 ,  H03K5/24 ,  H03K19/20 ,  G06F12/0802

CPC classification number: H03K5/24 ,  G06F7/026 ,  G06F12/0802 ,  G06F2212/60 ,  H03K19/20

Abstract: Disclosed systems and methods relate to comparison of a first number and a second number. A comparator receives first and second single-ended inputs (i.e., not represented in differential format), which may be n-bits wide, wherein the first input is an inverted version of the first number and the second input is a true version of the second number. A partial match circuit is implemented to generate a partial match output based only on the first single-ended input and the second single-ended input. A partial mismatch circuit is implemented to generate a partial mismatch output based only on the first single-ended input and the second single-ended input. A comparison output circuit is implemented to generate a comparison output of the first and second numbers based on the partial match output and the partial mismatch output.