公开(公告)号：US09251896B2

公开(公告)日：2016-02-02

申请号：US14257924

申请日：2014-04-21

Applicant: PANASONIC CORPORATION

Inventor： Yuichiro Ikeda ,  Kazuhiko Shimakawa ,  Yoshikazu Katoh ,  Ken Kawai

IPC: G11C13/00

CPC classification number: G11C13/0064 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/79

Abstract: In a method for writing into a variable resistance nonvolatile memory device according to one aspect of the present disclosure, a verify write operation of newly applying a voltage pulse for changing a resistance state is performed on a variable resistance element which does not satisfy a determination condition for verifying that the resistance state has been changed despite application of a voltage pulse for changing the resistance state, and the determination condition in the verify write operation is relaxed when an average number of times of verify write operation, having already been performed on all or part of a plurality of variable resistance elements that are targets for write operation, exceeds a predetermined number of times.

Abstract translation: 在根据本公开的一个方面的用于写入可变电阻非易失性存储器件的方法中，对不满足确定条件的可变电阻元件执行新施加用于改变电阻状态的电压脉冲的验证写入操作 用于验证电阻状态是否已经改变，尽管施加用于改变电阻状态的电压脉冲，并且当已经对所有或全部执行的验证写入操作的平均次数放松了验证写入操作中的确定条件 作为写入操作的目标的多个可变电阻元件的一部分超过预定次数。

公开(公告)号：US20140185360A1

公开(公告)日：2014-07-03

申请号：US14118635

申请日：2013-03-13

Applicant: Panasonic Corporation

Inventor： Ken Kawai ,  Kazuhiko Shimakawa ,  Yoshikazu Katoh

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0033 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/55

Abstract: A write method for writing to a variable resistance nonvolatile memory element, comprising applying a set of strong recovery-voltage pulses at least once to the variable resistance nonvolatile memory element when it is determined that the resistance state of the variable resistance nonvolatile memory element fails to change to a second resistance state, remaining in a first resistance state, the set of strong recovery-voltage pulses including pulses: (1) a first strong recovery-voltage pulse which has a greater amplitude than a normal second voltage for changing the resistance state to the first resistance state, and has the same polarity as the second voltage; and (2) a second strong recovery-voltage pulse which follows the first strong recovery-voltage pulse and has a longer pulse width than the pulse width of the normal first voltage for changing the resistance state to the second resistance state, and has the same polarity as the first voltage.

Abstract translation: 一种用于写入可变电阻非易失性存储元件的写入方法，包括当确定可变电阻非易失性存储元件的电阻状态不能够时，将至少一次的一组强恢复电压脉冲施加到可变电阻非易失性存储元件 改变为第二电阻状态，保持在第一电阻状态，包括脉冲的强恢复电压脉冲集合：（1）具有比用于改变电阻状态的正常第二电压更大的幅度的第一强恢复电压脉冲 并具有与第二电压相同的极性; 和（2）第二强恢复电压脉冲，其跟随第一强恢复电压脉冲并且具有比用于将电阻状态改变为第二电阻状态的正常第一电压的脉冲宽度更长的脉冲宽度，并且具有相同 极性作为第一电压。

公开(公告)号：US08885387B2

公开(公告)日：2014-11-11

申请号：US13990187

申请日：2012-11-21

Applicant: Panasonic Corporation

Inventor： Ryotaro Azuma ,  Kazuhiko Shimakawa

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: Each memory cell is formed at a different one of cross points of bit lines extending in an X direction and formed in a plurality of layers and word lines extending in a Y direction. In a multilayer cross point structure in which a plurality of vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements switch connection and disconnection between a global bit line and the commonly-connected even layer bit line and the commonly-connected odd layer bit line, respectively. Each of the even and odd layer bit line selection switch elements has both a bit line selection function and a current limiting function in low resistance writing.

Abstract translation: 每个存储单元形成在沿X方向延伸的位线的交叉点中的不同的一个，并且形成为沿Y方向延伸的多个层和字线。 在多个交叉点结构中，共享字线的多个垂直阵列平面在Y方向上对齐，对于在Z方向上排列的一组位线，偶数和奇数位线选择开关元件切换连接和断开 在全局位线和共同连接的偶数层位线和共同连接的奇数位位线之间。 偶数和奇数层位线选择开关元件中的每一个具有低电阻写入中的位线选择功能和限流功能。

公开(公告)号：US08848426B2

公开(公告)日：2014-09-30

申请号：US14047214

申请日：2013-10-07

Applicant: Panasonic Corporation

Inventor： Ryotaro Azuma ,  Kazuhiko Shimakawa

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/0064 ,  G11C2013/0042 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72

Abstract: A cross-point variable resistance nonvolatile memory device comprises: a memory cell array; a column decoder and pre-charge circuit which pre-charges a selected word line to a first voltage in a period P1 among the period P1, a period P2, and a period S that are included in this order in a read operation of a memory cell; a low decoder driver which pre-charges a selected word line to the first voltage in the periods P1 and P2 and sets the selected word line to a third voltage different from the first voltage in the period S; a feedback controlled bit line voltage clamp circuit which sets the selected bit line to a second voltage in the periods P2 and S; and a sense amplifier which determines the resistance state in a memory cell at a cross-point of the selected word line and the selected bit line in the period S.

Abstract translation: 交叉点可变电阻非易失性存储器件包括：存储单元阵列; 一个列解码器和预充电电路，其在周期P1，周期P2和周期S之间的周期P1中将所选择的字线预充电到第一电压，该周期P1，周期P2和周期S在存储器的读取操作中被依次包括 细胞; 低位解码器驱动器，其将所选择的字线预充电到时段P1和P2中的第一电压，并将所选择的字线设置为与周期S中的第一电压不同的第三电压; 反馈控制的位线电压钳位电路，其将所选择的位线设置在时段P2和S中的第二电压; 以及读出放大器，其确定在所选择的字线的交叉点和周期S中所选位线的存储器单元中的电阻状态。

公开(公告)号：US20140098594A1

公开(公告)日：2014-04-10

申请号：US13990187

申请日：2012-11-21

Applicant: PANASONIC CORPORATION

Inventor： Ryotaro Azuma ,  Kazuhiko Shimakawa

IPC: G11C13/00

CPC classification number: G11C13/0002 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/2418 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: Each memory cell is formed at a different one of cross points of bit lines extending in an X direction and formed in a plurality of layers and word lines extending in a Y direction. In a multilayer cross point structure in which a plurality of vertical array planes sharing the word lines are aligned in the Y direction each for a group of bit lines aligned in a Z direction, even and odd layer bit line selection switch elements switch connection and disconnection between a global bit line and the commonly-connected even layer bit line and the commonly-connected odd layer bit line, respectively. Each of the even and odd layer bit line selection switch elements has both a bit line selection function and a current limiting function in low resistance writing.

Abstract translation: 每个存储单元形成在沿X方向延伸的位线的交叉点中的不同的一个，并且形成为沿Y方向延伸的多个层和字线。 在多个交叉点结构中，共享字线的多个垂直阵列平面在Y方向上对齐，对于在Z方向上排列的一组位线，偶数和奇数位线选择开关元件切换连接和断开 在全局位线和共同连接的偶数层位线和共同连接的奇数位位线之间。 偶数和奇数层位线选择开关元件中的每一个具有低电阻写入中的位线选择功能和限流功能。

公开(公告)号：US20140078814A1

公开(公告)日：2014-03-20

申请号：US14119936

申请日：2013-03-27

Applicant: Panasonic Corporation

Inventor： Kazuhiko Shimakawa ,  Ryotaro Azuma ,  Yoshikazu Katoh ,  Akifumi Kawahara

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0083 ,  G11C2213/15

Abstract: The nonvolatile memory device includes a control circuit that controls a sense amplification circuit and a writing circuit. The control circuit changes a value of at least one of (a) a load current and (b) a forming pulse current or a forming pulse voltage, according to a total number of sneak current paths formed by memory cells each including a variable resistance element in a second resistance state having a low resistance value except a selected memory cell in a memory cell array.

Abstract translation: 非易失性存储器件包括控制读出放大电路和写入电路的控制电路。 控制电路根据由存储单元形成的每个包含可变电阻元件的总体潜流电流路径的总数，改变（a）负载电流和（b）形成脉冲电流或形成脉冲电压中的至少一个的值 在除了存储单元阵列中的所选存储单元之外具有低电阻值的第二电阻状态。

公开(公告)号：US09105332B2

公开(公告)日：2015-08-11

申请号：US14116482

申请日：2013-03-07

Applicant: Panasonic Corporation

Inventor： Yuichiro Ikeda ,  Kazuhiko Shimakawa ,  Koji Katayama ,  Takumi Mikawa ,  Kiyotaka Tsuji

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

Abstract: Provided is a variable resistance element (Rij) the resistance state of which is reversibly changed by applying electrical signals of different polarities; and a current steering element (Dij) in which a first current is larger than a second current, the first current being a current which flows when a voltage of the first polarity having a first value is applied, the first value being less than a predetermined voltage value and having an absolute value greater than zero, the second current being a current which flows when a voltage of the second polarity having an absolute value which is the first value is applied, the second polarity being different from the first polarity, in which Rij and Dij are connected in series such that the polarity of a voltage to be applied to Dij is the second polarity when the resistance state of Rij is changed to high resistance state.

Abstract translation: 提供通过施加不同极性的电信号可逆地改变其电阻状态的可变电阻元件（Rij）; 以及电流控制元件（Dij），其中第一电流大于第二电流，所述第一电流是当施加具有第一值的第一极性的电压时流动的电流，所述第一值小于预定的 电压值，绝对值大于零，第二电流是当施加具有作为第一值的绝对值的第二极性的电压时流过的电流，第二极性与第一极性不同，其中 Rij和Dij串联连接，使得当Rij的电阻状态变为高电阻状态时，施加到Dij的电压的极性是第二极性。

公开(公告)号：US09064573B2

公开(公告)日：2015-06-23

申请号：US14229365

申请日：2014-03-28

Applicant: PANASONIC CORPORATION

Inventor： Ken Kawai ,  Kazuhiko Shimakawa ,  Yoshikazu Katoh

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0064 ,  G11C2013/0042 ,  G11C2013/0054 ,  G11C2213/79

Abstract: A writing method of a variable resistance non-volatile memory element comprises determining, in a first determination step, whether or not a resistance state of the variable resistance non-volatile memory element does not switch to a first resistance state and remains in a second resistance state, when a pulse of a second voltage is applied to the variable resistance non-volatile memory element; and when it is determined that the resistance state of the variable resistance non-volatile memory element does not switch to the first resistance state and remains in the second resistance state in the first determination step, applying, in a recovery step, at least once to the variable-resistance non-volatile memory element a recovery voltage pulse set composed of two pulses which are a first recovery voltage pulse which has the same polarity as that of the first voltage and a second recovery voltage pulse which has the same polarity as that of the second voltage, has a greater amplitude than the second voltage, and is applied subsequently to the first recovery voltage pulse.

Abstract translation: 可变电阻非易失性存储元件的写入方法包括在第一确定步骤中确定可变电阻非易失性存储元件的电阻状态是否不转换到第一电阻状态并保持在第二电阻 当第二电压的脉冲施加到可变电阻非易失性存储元件时; 并且当在第一确定步骤中确定可变电阻非易失性存储元件的电阻状态不转换到第一电阻状态并保持在第二电阻状态时，在恢复步骤中至少一次至 所述可变电阻非易失性存储元件是由作为与所述第一电压具有相同极性的第一恢复电压脉冲和具有与所述第一电压相同极性的第二恢复电压脉冲的两个脉冲组成的恢复电压脉冲， 第二电压具有比第二电压更大的幅度，并且随后施加到第一恢复电压脉冲。

公开(公告)号：US08848424B2

公开(公告)日：2014-09-30

申请号：US13976172

申请日：2012-11-15

Applicant: Panasonic Corporation

Inventor： Yuichiro Ikeda ,  Kazuhiko Shimakawa ,  Ryotaro Azuma

IPC: G11C11/00 ,  G11C13/00 ,  H01L27/24 ,  H01L27/10

CPC classification number: G11C13/003 ,  G11C13/00 ,  G11C13/0007 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: A variable resistance nonvolatile memory device includes: bit lines in layers; word lines in layers formed at intervals between the layers of the bit lines; a memory cell array including basic array planes and having memory cells formed at crosspoints of the bit lines in the layers and the word lines in the layers; global bit lines provided in one-to-one correspondence with the basic array planes; and sets provided in one-to-one correspondence with the basic array planes, and each including a first selection switch element and a second selection switch element, wherein memory cells connected to the same word line are successively accessed in different basic array planes, and memory cells are selected so that voltages applied to the word line and bit lines are not changed and a direction in which current flows through the memory cells is the same.

Abstract translation: 可变电阻非易失性存储器件包括：位线; 位线之间的间隔形成的字线; 存储单元阵列，包括基本阵列平面，并且具有在层中的位线和层中的字线的交叉点处形成的存储器单元; 提供与基本阵列平面一一对应的全局位线; 并且与基本阵列平面一一对应地设置，并且每个包括第一选择开关元件和第二选择开关元件，其中连接到相同字线的存储器单元在不同的基本阵列平面中被连续地访问，并且 选择存储单元，使得施加到字线和位线的电压不改变，并且电流流过存储器单元的方向相同。

公开(公告)号：US20140126267A1

公开(公告)日：2014-05-08

申请号：US14116482

申请日：2013-03-07

Applicant: Panasonic Corporation

Inventor： Yuichiro Ikeda ,  Kazuhiko Shimakawa ,  Koji Katayama ,  Takumi Mikawa ,  Kiyotaka Tsuji

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1675

Abstract: Provided is a variable resistance element (Rij) the resistance state of which is reversibly changed by applying electrical signals of different polarities; and a current steering element (Dij) in which a first current is larger than a second current, the first current being a current which flows when a voltage of the first polarity having a first value is applied, the first value being less than a predetermined voltage value and having an absolute value greater than zero, the second current being a current which flows when a voltage of the second polarity having an absolute value which is the first value is applied, the second polarity being different from the first polarity, in which Rij and Dij are connected in series such that the polarity of a voltage to be applied to Dij is the second polarity when the resistance state of Rij is changed to high resistance state.

Abstract translation: 提供通过施加不同极性的电信号可逆地改变其电阻状态的可变电阻元件（Rij）; 以及电流控制元件（Dij），其中第一电流大于第二电流，所述第一电流是当施加具有第一值的第一极性的电压时流动的电流，所述第一值小于预定的 电压值，绝对值大于零，第二电流是当施加具有作为第一值的绝对值的第二极性的电压时流过的电流，第二极性与第一极性不同，其中 Rij和Dij串联连接，使得当Rij的电阻状态变为高电阻状态时，施加到Dij的电压的极性是第二极性。