公开(公告)号：US08722497B2

公开(公告)日：2014-05-13

申请号：US13953704

申请日：2013-07-29

Applicant: Nissan Motor Co., Ltd. ,  Rohm Co., Ltd.

Inventor： Satoshi Tanimoto ,  Noriaki Kawamoto ,  Takayuki Kitou ,  Mineo Miura

IPC: H01L29/24

CPC classification number: H01L29/66068 ,  H01L21/049 ,  H01L21/31666 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7395 ,  H01L29/7802

Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).

Abstract translation: 碳化硅半导体器件（90）包括：1）碳化硅衬底（1）; 2）由多晶硅制成的栅电极（7） 和3）夹在所述碳化硅衬底（1）和所述栅电极（7）之间的ONO绝缘膜（9），从而形成栅极结构，所述ONO绝缘膜（9）包括从所述碳化硅衬底 （1）：a）第一氧化硅膜（O）（10），b）SiN膜（N）（11），和c）SiN热氧化膜（O）（12,12a，12b）。 氮在以下位置中的至少一个中包括：i）在第一氧化物硅膜（O）（10）中和在碳化硅衬底（1）附近，以及ii）在碳化硅衬底 （1）和第一氧化硅膜（O）（10）。

公开(公告)号：US08716087B2

公开(公告)日：2014-05-06

申请号：US13953693

申请日：2013-07-29

Applicant: Nissan Motor Co., Ltd. ,  Rohm Co., Ltd.

Inventor： Satoshi Tanimoto ,  Noriaki Kawamoto ,  Takayuki Kitou ,  Mineo Miura

IPC: H01L29/24

CPC classification number: H01L29/66068 ,  H01L21/049 ,  H01L21/31666 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/518 ,  H01L29/7395 ,  H01L29/7802

Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).

公开(公告)号：US11367738B2

公开(公告)日：2022-06-21

申请号：US17109676

申请日：2020-12-02

Applicant: ROHM CO., LTD.

Inventor： Katsuhisa Nagao ,  Noriaki Kawamoto

IPC: H01L27/07 ,  H01L27/118 ,  H01L29/16 ,  H01L29/739 ,  H01L29/423 ,  H01L29/78 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10 ,  H01L23/532

Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.

公开(公告)号：US10886300B2

公开(公告)日：2021-01-05

申请号：US16555843

申请日：2019-08-29

Applicant: ROHM CO., LTD.

Inventor： Katsuhisa Nagao ,  Noriaki Kawamoto

IPC: H01L27/07 ,  H01L27/118 ,  H01L29/16 ,  H01L29/739 ,  H01L29/423 ,  H01L29/78 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10 ,  H01L23/532

Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.

公开(公告)号：US10438971B2

公开(公告)日：2019-10-08

申请号：US15883690

申请日：2018-01-30

Applicant: ROHM CO., LTD.

Inventor： Katsuhisa Nagao ,  Noriaki Kawamoto

IPC: H01L23/522 ,  H01L27/118 ,  H01L29/16 ,  H01L29/739 ,  H01L29/423 ,  H01L29/78 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10 ,  H01L23/532

Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electron (19) together.

公开(公告)号：US09917102B2

公开(公告)日：2018-03-13

申请号：US15039725

申请日：2014-11-26

Applicant: ROHM CO., LTD.

Inventor： Katsuhisa Nagao ,  Noriaki Kawamoto

IPC: H01L29/66 ,  H01L27/118 ,  H01L29/16 ,  H01L29/739 ,  H01L29/423 ,  H01L29/78 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10 ,  H01L23/532

CPC classification number: H01L27/11898 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L27/11807 ,  H01L27/11896 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/78 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2027/11866

Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside: and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.

公开(公告)号：US11908868B2

公开(公告)日：2024-02-20

申请号：US17748633

申请日：2022-05-19

Applicant: ROHM CO., LTD.

Inventor： Katsuhisa Nagao ,  Noriaki Kawamoto

IPC: H01L29/06 ,  H01L27/118 ,  H01L29/16 ,  H01L29/739 ,  H01L29/423 ,  H01L29/78 ,  H01L23/528 ,  H01L29/10 ,  H01L23/532

CPC classification number: H01L27/11898 ,  H01L23/528 ,  H01L27/11807 ,  H01L27/11896 ,  H01L29/1608 ,  H01L29/42372 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7813 ,  H01L23/53214 ,  H01L23/53219 ,  H01L23/53228 ,  H01L23/53233 ,  H01L29/0615 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/78 ,  H01L2027/11866

Abstract: A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.

公开(公告)号：US10727318B2

公开(公告)日：2020-07-28

申请号：US15261830

申请日：2016-09-09

Applicant: ROHM CO., LTD.

Inventor： Keiji Okumura ,  Mineo Miura ,  Yuki Nakano ,  Noriaki Kawamoto ,  Hidetoshi Abe

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/51 ,  H01L29/423 ,  H01L29/08 ,  H01L21/02 ,  H01L21/311 ,  H01L29/16 ,  H01L29/45

Abstract: A method for producing a semiconductor power device, includes forming a gate trench from a surface of a semiconductor layer toward an inside thereof. A first insulation film is formed on an inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.