公开(公告)号：US20100128536A1

公开(公告)日：2010-05-27

申请号：US12594595

申请日：2008-04-01

Applicant: Nader Akil ,  Michiel Van Duuren

Inventor： Nader Akil ,  Michiel Van Duuren

IPC: G11C16/04

CPC classification number: G11C16/0466 ,  G11C16/0433

Abstract: A method of programming a memory cell (100), the method comprising applying a first electric potential to a first electric terminal (101) of the memory cell (100) to accelerate first charge carriers of a first type of conductivity to thereby generate second charge carriers of a second type of conductivity by impact ionisation of the accelerated first charge carriers, and applying a second electric potential to a second electric terminal (102) of the memory cell (100) to accelerate the second charge carriers to thereby inject the second charge carriers in a charge trapping structure (103) of the memory cell (100).

Abstract translation: 一种对存储单元（100）进行编程的方法，所述方法包括：向所述存储单元（100）的第一电端（101）施加第一电位，以加速第一导电类型的第一电荷载流子，从而产生第二电荷 通过加速的第一电荷载流子的冲击电离使第二类型的导电性的载流子，以及向存储单元（100）的第二电端子（102）施加第二电位，以加速第二电荷载流子，从而注入第二电荷 存储单元（100）的电荷俘获结构（103）中的载流子。

公开(公告)号：US08320192B2

公开(公告)日：2012-11-27

申请号：US12594595

申请日：2008-04-01

Applicant: Nader Akil ,  Michiel Van Duuren

Inventor： Nader Akil ,  Michiel Van Duuren

IPC: G11C11/34

CPC classification number: G11C16/0466 ,  G11C16/0433

Abstract: A method of programming a memory cell (100), the method comprising applying a first electric potential to a first electric terminal (101) of the memory cell (100) to accelerate first charge carriers of a first type of conductivity to thereby generate second charge carriers of a second type of conductivity by impact ionisation of the accelerated first charge carriers, and applying a second electric potential to a second electric terminal (102) of the memory cell (100) to accelerate the second charge carriers to thereby inject the second charge carriers in a charge trapping structure (103) of the memory cell (100).

Abstract translation: 一种对存储单元（100）进行编程的方法，所述方法包括：向所述存储单元（100）的第一电端（101）施加第一电位，以加速第一导电类型的第一电荷载流子，从而产生第二电荷 通过加速的第一电荷载流子的冲击电离使第二类型的导电性的载流子，以及向存储单元（100）的第二电端子（102）施加第二电位，以加速第二电荷载流子，从而注入第二电荷 存储单元（100）的电荷俘获结构（103）中的载流子。

公开(公告)号：US08794054B2

公开(公告)日：2014-08-05

申请号：US13262628

申请日：2010-03-25

Applicant: Evelyne Gridelet ,  Pablo Garcia Tello ,  Michiel Jos Van Duuren ,  Nader Akil

Inventor： Evelyne Gridelet ,  Pablo Garcia Tello ,  Michiel Jos Van Duuren ,  Nader Akil

IPC: G01N29/036

CPC classification number: G01N33/5438 ,  B81C1/00087 ,  G01N33/48721

Abstract: A sensor device for analyzing fluidic samples is provided. The sensor device includes a stacked sensing arrangement having at least three sensing layers and a multilayer structure. The multilayer structure has a hole formed therein which is adapted to let pass the fluidic sample and the stacked sensing arrangement is formed in the multilayer structure in such a way that the fluidic sample passes the stacked sensing arrangement when the fluidic sample passes the hole.

Abstract translation: 提供了一种用于分析流体样品的传感器装置。 传感器装置包括具有至少三个感测层和多层结构的层叠感测装置。 多层结构具有形成在其中的孔，其适于使流体样品通过，并且层叠的感测装置形成在多层结构中，使得当流体样品通过孔时流体样品通过堆叠的感测装置。

公开(公告)号：US09287414B2

公开(公告)日：2016-03-15

申请号：US13499805

申请日：2010-10-21

Applicant: Georgios Vellianitis ,  Gilberto Curatola ,  Kyriaki Fotopoulou ,  Nader Akil

Inventor： Georgios Vellianitis ,  Gilberto Curatola ,  Kyriaki Fotopoulou ,  Nader Akil

IPC: H01L29/872 ,  H01L21/20 ,  H01L29/66 ,  H01L27/06 ,  H01L29/08

CPC classification number: H01L29/872 ,  H01L27/0629 ,  H01L29/083 ,  H01L29/66143

Abstract: An integrated circuit including a Schottky diode, and a method of making the same. The diode includes an active region bordered by an isolation region in a semiconductor substrate of the integrated circuits, a first electrode having a metal contact provided on a surface of the active region, and a second electrode having a silicide contact also provided on the surface of the active region.

Abstract translation: 包括肖特基二极管的集成电路及其制造方法。 二极管包括由集成电路的半导体衬底中的隔离区域界定的有源区，具有设置在有源区的表面上的金属接触的第一电极和还具有硅化物接触的第二电极， 活跃区域。

公开(公告)号：US08546863B2

公开(公告)日：2013-10-01

申请号：US12594673

申请日：2008-04-17

Applicant: Almudena Huerta ,  Michiel Jos Van Duuren ,  Nader Akil ,  Dusan Golubovic ,  Mohamed Boutchich

Inventor： Almudena Huerta ,  Michiel Jos Van Duuren ,  Nader Akil ,  Dusan Golubovic ,  Mohamed Boutchich

IPC: H01L29/76 ,  H01L21/336

CPC classification number: B82Y10/00 ,  G11C16/0433 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0203 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

Abstract: A memory cell, the memory cell comprising a substrate, a nanowire extending along a vertical trench formed in the substrate, a control gate surrounding the nanowire, and a charge storage structure formed between the control gate and the nanowire.

Abstract translation: 存储单元，所述存储单元包括衬底，沿着形成在所述衬底中的垂直沟槽延伸的纳米线，围绕所述纳米线的控制栅极以及形成在所述控制栅极和所述纳米线之间的电荷存储结构。

公开(公告)号：US08334559B2

公开(公告)日：2012-12-18

申请号：US12780612

申请日：2010-05-14

Applicant: Nader Akil ,  Michiel J. Van Duuren

Inventor： Nader Akil ,  Michiel J. Van Duuren

IPC: H01L29/788

CPC classification number: H01L29/42324 ,  H01L29/7881

Abstract: A semiconductor storage device includes a semiconductor substrate having a first region of a first conductivity type in between respective regions of an opposite conductivity type, at least the first region being covered by a first dielectric layer, a polysilicon floating gate placed on the first dielectric layer over the first region, said floating gate being surrounded by an insulating material; and a metal control gate structure adjacent to the polysilicon floating gate, the metal control gate structure being capacitively coupled to said floating gate. A method of manufacturing such a semiconductor storage device is also disclosed.

Abstract translation: 一种半导体存储装置，包括具有第一导电类型的第一区域的相应导电类型的相应区域之间的至少第一区域被第一介电层覆盖的半导体衬底，放置在第一介电层上的多晶硅浮置栅极 在第一区域上，所述浮栅被绝缘材料包围; 以及与所述多晶硅浮置栅极相邻的金属控制栅极结构，所述金属控制栅极结构电容耦合到所述浮置栅极。 还公开了制造这种半导体存储装置的方法。

公开(公告)号：US20120199937A1

公开(公告)日：2012-08-09

申请号：US13499805

申请日：2010-10-21

Applicant: Georgios Vellianitis ,  Gilberto Curatola ,  Kyriaki Fotopoulou ,  Nader Akil

Inventor： Georgios Vellianitis ,  Gilberto Curatola ,  Kyriaki Fotopoulou ,  Nader Akil

IPC: H01L29/47 ,  H01L21/20 ,  H01L21/329

CPC classification number: H01L29/872 ,  H01L27/0629 ,  H01L29/083 ,  H01L29/66143

Abstract: An integrated circuit including a Schottky diode, and a method of making the same. The diode includes an active region bordered by an isolation region in a semiconductor substrate of the integrated circuits, a first electrode having a metal contact provided on a surface of the active region, and a second electrode having a silicide contact also provided on the surface of the active region.

Abstract translation: 包括肖特基二极管的集成电路及其制造方法。 二极管包括由集成电路的半导体衬底中的隔离区域界定的有源区，具有设置在有源区的表面上的金属接触的第一电极和还具有硅化物接触的第二电极， 活跃区域。

公开(公告)号：US20120060589A1

公开(公告)日：2012-03-15

申请号：US13262628

申请日：2010-03-25

Applicant: Evelyne Gridelet ,  Pablo Garcia Tello ,  Michiel Jos Van Duuren ,  Nader Akil

Inventor： Evelyne Gridelet ,  Pablo Garcia Tello ,  Michiel Jos Van Duuren ,  Nader Akil

IPC: G01N27/26 ,  H05K13/00 ,  B23P17/04

CPC classification number: G01N33/5438 ,  B81C1/00087 ,  G01N33/48721

Abstract: A sensor device for analyzing fluidic samples is provided, wherein the sensor device comprises a stacked sensing arrangement comprising at least three sensing layers and a multilayer structure, wherein the multilayer structure has a hole formed therein which is adapted to let pass the fluidic sample and wherein the stacked sensing arrangement is formed in the multilayer structure in such a way that the fluidic sample passes the stacked sensing arrangement when the fluidic sample passes the hole.

Abstract translation: 提供了一种用于分析流体样品的传感器装置，其中所述传感器装置包括包括至少三个感测层和多层结构的堆叠感测装置，其中所述多层结构具有形成在其中的孔，其适于使所述流体样品通过，并且其中 层叠的感测装置形成在多层结构中，使得当流体样品通过孔时，流体样品通过堆叠的感测装置。

公开(公告)号：US20100308394A1

公开(公告)日：2010-12-09

申请号：US12780612

申请日：2010-05-14

Applicant: Nader Akil ,  Michiel J. Van Duuren

Inventor： Nader Akil ,  Michiel J. Van Duuren

IPC: H01L29/788 ,  H01L21/28

CPC classification number: H01L29/42324 ,  H01L29/7881

Abstract: A semiconductor storage device includes a semiconductor substrate having a first region of a first conductivity type in between respective regions of an opposite conductivity type, at least the first region being covered by a first dielectric layer, a polysilicon floating gate placed on the first dielectric layer over the first region, said floating gate being surrounded by an insulating material; and a metal control gate structure adjacent to the polysilicon floating gate, the metal control gate structure being capacitively coupled to said floating gate. A method of manufacturing such a semiconductor storage device is also disclosed.

Abstract translation: 一种半导体存储装置，包括具有第一导电类型的第一区域的相应导电类型的相应区域之间的至少第一区域被第一介电层覆盖的半导体衬底，放置在第一介电层上的多晶硅浮置栅极 在第一区域上，所述浮栅被绝缘材料包围; 以及与所述多晶硅浮置栅极相邻的金属控制栅极结构，所述金属控制栅极结构电容耦合到所述浮置栅极。 还公开了制造这种半导体存储装置的方法。

公开(公告)号：US20120228717A1

公开(公告)日：2012-09-13

申请号：US13500405

申请日：2010-11-17

Applicant: Georgios Vellianitis ,  Gilberto Curatola ,  Kyriaki Fotopoulou ,  Nader Akil

Inventor： Georgios Vellianitis ,  Gilberto Curatola ,  Kyriaki Fotopoulou ,  Nader Akil

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0629 ,  H01L27/0814 ,  H01L27/095 ,  H01L29/66143 ,  H01L29/872

Abstract: A method of manufacturing Schottky diodes in a CMOS process includes forming wells, including first wells (16) for forming CMOS devices and second wells (18) for forming Schottky devices. Then, transistors arc formed in the first wells, the second wells protected with a protection layer (20) and suicide contacts (40) formed to source and drain regions in the first wells. The protection layer is then removed, a Schottky material deposited and etched away except in a contact region in each second well to form a Schottky contact between the Schottky material (74) and each second well (18).

Abstract translation: 在CMOS工艺中制造肖特基二极管的方法包括形成阱，包括用于形成CMOS器件的第一阱（16）和用于形成肖特基器件的第二阱（18）。 然后，在第一阱中形成晶体管，第二阱由保护层（20）和形成于第一阱中的源极和漏极区域的硅化物触点（40）保护。 然后去除保护层，除了在每个第二阱中的接触区域中沉积并蚀刻掉肖特基材料，以在肖特基材料（74）和每个第二阱（18）之间形成肖特基接触。