公开(公告)号：US20220121485A1

公开(公告)日：2022-04-21

申请号：US17075013

申请日：2020-10-20

申请人： Micron Technology, Inc.

发明人： Chris Baronne ,  Dean E. Walker ,  John Amelio

IPC分类号： G06F9/48 ,  G06F1/10 ,  G06F12/0875

摘要： Devices and techniques for thread replay to preserve state in a barrel processor are described herein. An apparatus includes a barrel processor, which includes a temporary memory; and a thread scheduling circuitry; wherein the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including those to: schedule a current thread to place into a pipeline for the barrel processor on a clock cycle, the barrel processor to schedule threads on each clock cycle; store the current thread in the temporary memory; detect that no thread is available on a clock cycle subsequent to the cycle that the current thread is scheduled; and in response to detecting that no thread is available on the subsequent clock cycle, repeat scheduling the current thread based on the contents of the temporary memory.

公开(公告)号：US12020064B2

公开(公告)日：2024-06-25

申请号：US17075051

申请日：2020-10-20

申请人： Micron Technology, Inc.

发明人： Chris Baronne ,  Dean E. Walker ,  John Amelio

IPC分类号： G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F13/16 ,  G06F9/54 ,  G06F12/0804

CPC分类号： G06F9/4881 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/38 ,  G06F9/3858 ,  G06F11/3037 ,  G06F13/1668 ,  G06F9/3834 ,  G06F9/3873 ,  G06F9/546 ,  G06F12/0804

摘要： Devices and techniques to reschedule a memory request that has failed when a thread is executing in a processor are described herein. When a memory request for a thread is denied at a point in the execution pipeline of the processor beyond a thread rescheduling point, the thread can be placed into a memory response path of the processor. An indicator that a register write-back will not occur for the thread can also be provided. Then, the thread can be rescheduled with other threads in the memory response path.

公开(公告)号：US20220121487A1

公开(公告)日：2022-04-21

申请号：US17075096

申请日：2020-10-20

申请人： Micron Technology, Inc.

发明人： Chris Baronne ,  Dean E. Walker ,  John Amelio

IPC分类号： G06F9/48 ,  G06F9/30 ,  G11C7/10 ,  G11C7/22

摘要： Devices and techniques for thread scheduling control and memory splitting in a barrel processor are described herein. An apparatus includes a barrel processor, which includes thread scheduling circuitry, where the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including those to: place a thread to be scheduled in one of two groups: a first group and a second group, wherein the first group is associated with a first processor storage device, and the second group is associated with a second processor storage device; and schedule a current thread to place into a pipeline for the barrel processor, the scheduling performed by alternating between threads in the first group and threads in the second group.

公开(公告)号：US20220121486A1

公开(公告)日：2022-04-21

申请号：US17075051

申请日：2020-10-20

申请人： Micron Technology, Inc.

发明人： Chris Baronne ,  Dean E. Walker ,  John Amelio

IPC分类号： G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F9/54 ,  G06F13/16 ,  G06F11/30

摘要： Devices and techniques for rescheduling a failed memory request in a processor are described herein. When a memory request for a thread is denied at a point in the execution pipeline of the processor beyond a thread rescheduling point, the thread can be placed into a memory response path of the processor. An indicator that a register write-back will not occur for the thread can also be provided. Then, the thread can be rescheduled with other threads in the memory response path.

公开(公告)号：US20220382557A1

公开(公告)日：2022-12-01

申请号：US17880230

申请日：2022-08-03

申请人： Micron Technology, Inc.

发明人： Dean E. Walker ,  Tony Brewer ,  Chris Baronne

IPC分类号： G06F9/4401 ,  G06F12/14

摘要： Devices and techniques for on-demand programmable atomic kernel loading are described herein. A programmable atomic unit (PAU) of a memory controller can receive an invocation of a programmable atomic operator by the memory controller. The PAU can then perform a verification on a programmable atomic operator partition for the programmable atomic operator. Here, the programmable atomic operator partition is located in a memory of the PAU. The PAU can then signal a trap in response to the verification indicating that the programmable atomic operator partition is not prepared.

公开(公告)号：US11379365B2

公开(公告)日：2022-07-05

申请号：US17075073

申请日：2020-10-20

申请人： Micron Technology, Inc.

发明人： Tony Brewer ,  Dean E. Walker ,  Chris Baronne

IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F12/02 ,  G06F12/0844

摘要： Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.

公开(公告)号：US20220121567A1

公开(公告)日：2022-04-21

申请号：US17075073

申请日：2020-10-20

申请人： Micron Technology, Inc.

发明人： Tony Brewer ,  Dean E. Walker ,  Chris Baronne

IPC分类号： G06F12/06

摘要： Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.

公开(公告)号：US20220121452A1

公开(公告)日：2022-04-21

申请号：US17075055

申请日：2020-10-20

申请人： Micron Technology, Inc.

发明人： Dean E. Walker ,  Tony Brewer ,  Chris Baronne

IPC分类号： G06F9/4401 ,  G06F12/14

摘要： Devices and techniques for on-demand programmable atomic kernel loading are described herein. A programmable atomic unit (PAU) of a memory controller can receive an invocation of a programmable atomic operator by the memory controller. The PAU can then perform a verification on a programmable atomic operator partition for the programmable atomic operator. Here, the programmable atomic operator partition is located in a memory of the PAU. The PAU can then signal a trap in response to the verification indicating that the programmable atomic operator partition is not prepared.

公开(公告)号：US11734173B2

公开(公告)日：2023-08-22

申请号：US17854770

申请日：2022-06-30

申请人： Micron Technology, Inc.

发明人： Tony Brewer ,  Dean E. Walker ,  Chris Baronne

IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F12/02 ,  G06F12/0844

CPC分类号： G06F12/0607 ,  G06F12/0223 ,  G06F12/0844 ,  G06F2212/1012

摘要： Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.

公开(公告)号：US11698791B2

公开(公告)日：2023-07-11

申请号：US17880230

申请日：2022-08-03

申请人： Micron Technology, Inc.

发明人： Dean E. Walker ,  Tony Brewer ,  Chris Baronne

IPC分类号： G06F9/4401 ,  G06F12/14

CPC分类号： G06F9/4403 ,  G06F12/1458 ,  G06F12/14 ,  G06F2212/1052 ,  Y02D10/00

摘要： Devices and techniques for on-demand programmable atomic kernel loading are described herein. A programmable atomic unit (PAU) of a memory controller can receive an invocation of a programmable atomic operator by the memory controller. The PAU can then perform a verification on a programmable atomic operator partition for the programmable atomic operator. Here, the programmable atomic operator partition is located in a memory of the PAU. The PAU can then signal a trap in response to the verification indicating that the programmable atomic operator partition is not prepared.