公开(公告)号：US20220121483A1

公开(公告)日：2022-04-21

申请号：US17074920

申请日：2020-10-20

申请人： Micron Technology, Inc.

发明人： Chris Baronne ,  Dean E. Walker ,  John Amelio

IPC分类号： G06F9/48 ,  G06F12/0802 ,  G06F9/38 ,  G06F9/50

摘要： Devices and techniques for thread execution control in a barrel processor are described herein. An apparatus includes a barrel processor, which includes local memory including a hazard data structure; and thread scheduling circuitry; wherein the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including: identifying an instruction to place into a pipeline for the barrel processor, the instruction corresponding to a thread; reading a hazard indication entry from a hazard data structure, the hazard indication entry corresponding to the thread, and wherein the hazard indication entry is set by a preceding instruction in the thread; and in response to reading the hazard indication entry, rescheduling the thread to a later time based on the hazard identification.

公开(公告)号：US20220121485A1

公开(公告)日：2022-04-21

申请号：US17075013

申请日：2020-10-20

申请人： Micron Technology, Inc.

发明人： Chris Baronne ,  Dean E. Walker ,  John Amelio

IPC分类号： G06F9/48 ,  G06F1/10 ,  G06F12/0875

摘要： Devices and techniques for thread replay to preserve state in a barrel processor are described herein. An apparatus includes a barrel processor, which includes a temporary memory; and a thread scheduling circuitry; wherein the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including those to: schedule a current thread to place into a pipeline for the barrel processor on a clock cycle, the barrel processor to schedule threads on each clock cycle; store the current thread in the temporary memory; detect that no thread is available on a clock cycle subsequent to the cycle that the current thread is scheduled; and in response to detecting that no thread is available on the subsequent clock cycle, repeat scheduling the current thread based on the contents of the temporary memory.

公开(公告)号：US12020064B2

公开(公告)日：2024-06-25

申请号：US17075051

申请日：2020-10-20

申请人： Micron Technology, Inc.

发明人： Chris Baronne ,  Dean E. Walker ,  John Amelio

IPC分类号： G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F11/30 ,  G06F13/16 ,  G06F9/54 ,  G06F12/0804

CPC分类号： G06F9/4881 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/38 ,  G06F9/3858 ,  G06F11/3037 ,  G06F13/1668 ,  G06F9/3834 ,  G06F9/3873 ,  G06F9/546 ,  G06F12/0804

摘要： Devices and techniques to reschedule a memory request that has failed when a thread is executing in a processor are described herein. When a memory request for a thread is denied at a point in the execution pipeline of the processor beyond a thread rescheduling point, the thread can be placed into a memory response path of the processor. An indicator that a register write-back will not occur for the thread can also be provided. Then, the thread can be rescheduled with other threads in the memory response path.

公开(公告)号：US20220121487A1

公开(公告)日：2022-04-21

申请号：US17075096

申请日：2020-10-20

申请人： Micron Technology, Inc.

发明人： Chris Baronne ,  Dean E. Walker ,  John Amelio

IPC分类号： G06F9/48 ,  G06F9/30 ,  G11C7/10 ,  G11C7/22

摘要： Devices and techniques for thread scheduling control and memory splitting in a barrel processor are described herein. An apparatus includes a barrel processor, which includes thread scheduling circuitry, where the barrel processor is configured to perform operations through use of the thread scheduling circuitry, the operations including those to: place a thread to be scheduled in one of two groups: a first group and a second group, wherein the first group is associated with a first processor storage device, and the second group is associated with a second processor storage device; and schedule a current thread to place into a pipeline for the barrel processor, the scheduling performed by alternating between threads in the first group and threads in the second group.

公开(公告)号：US20220121486A1

公开(公告)日：2022-04-21

申请号：US17075051

申请日：2020-10-20

申请人： Micron Technology, Inc.

发明人： Chris Baronne ,  Dean E. Walker ,  John Amelio

IPC分类号： G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F9/54 ,  G06F13/16 ,  G06F11/30

摘要： Devices and techniques for rescheduling a failed memory request in a processor are described herein. When a memory request for a thread is denied at a point in the execution pipeline of the processor beyond a thread rescheduling point, the thread can be placed into a memory response path of the processor. An indicator that a register write-back will not occur for the thread can also be provided. Then, the thread can be rescheduled with other threads in the memory response path.